参数资料
型号: ICS8421002AGIT
厂商: INTEGRATED DEVICE TECHNOLOGY INC
元件分类: 时钟产生/分配
英文描述: 226.66 MHz, OTHER CLOCK GENERATOR, PDSO20
封装: 6.50 X 4.40 MM, 0.92 MM HEIGHT, MO-153, TSSOP-20
文件页数: 14/15页
文件大小: 1085K
代理商: ICS8421002AGIT
IDT / ICS HSTL FREQUENCY SYNTHESIZER
8
ICS8421002I REV B AUGUST 7, 2006
ICS8421002I
FEMTOCLOCKS CRYSTAL-TO-HSTL FREQUENCY SYNTHESIZER
CRYSTAL INPUT INTERFACE
The ICS8421002I has been characterized with 18pF parallel
resonant crystals. The capacitor values shown in
Figure 2 below
Figure 2. CRYSTAL INPUt INTERFACE
were determined using a 26.5625MHz 18pF parallel resonant
crystal and were chosen to minimize the ppm error.
APPLICATION INFORMATION
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS8421002I provides
separate power supplies to isolate any high switching
noise from the outputs to the internal PLL. V
DD, VDDA, and VDDO
should be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance, power
supply isolation is required.
Figure 1 illustrates how
a 10
resistor along with a 10F and a .01F bypass
capacitor should be connected to each V
DDA.
POWER SUPPLY FILTERING TECHNIQUES
FIGURE 1. POWER SUPPLY FILTERING
10
V
DDA
10
F
.01
F
3.3V or 2.5V
.01
F
V
DD
C1
22p
X1
18pF Parallel Crystal
C2
22p
XTAL_OUT
XTAL_IN
INPUTS:
CRYSTAL INPUT:
For applications not requiring the use of the crystal oscillator input,
both XTAL_IN and XTAL_OUT can be left floating. Though not
required, but for additional protection, a 1k
resistor can be tied
from XTAL_IN to ground.
REF_CLK INPUT:
For applications not requiring the use of the reference clock,
it can be left floating. Though not required, but for additional
protection, a 1k
resistor can be tied from the REF_CLK to
ground.
LVCMOS CONTROL PINS:
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1k
resistor can be used.
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
OUTPUTS:
HSTL OUTPUT
All unused HSTL outputs can be left floating. We recommend
that there is no trace attached. Both sides of the differential output
pair should either be left floating or terminated.
相关PDF资料
PDF描述
ICS8421004AGI-01T 170 MHz, OTHER CLOCK GENERATOR, PDSO24
ICS8421004AGI-01 170 MHz, OTHER CLOCK GENERATOR, PDSO24
ICS8421004AGI-01LF 170 MHz, OTHER CLOCK GENERATOR, PDSO24
ICS8421004AGILF 226.66 MHz, OTHER CLOCK GENERATOR, PDSO24
ICS8421004AGILF 226.66 MHz, OTHER CLOCK GENERATOR, PDSO24
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