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参数资料
| 型号： | ICS843003AGLF |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 700 MHz, OTHER CLOCK GENERATOR, PDSO24 |
| 封装： | 4.40 X 7.80 MM, 0.925 MM HEIGHT, ROHS COMPLIANT, MO-153, TSSOP-24 |
| 文件页数： | 12/21页 |
| 文件大小： | 1125K |
| 代理商： | ICS843003AGLF |
ICS843003
FEMTOCLOCKS CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
IDT / ICS LVPECL FREQUENCY SYNTHESIZER
2
ICS843003AG REV. A FEBRUARY 19, 2008
Table 1. Pin Descriptions
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Number
Name
Type
Description
1
DIV_SELB0
Input
Pulldown
Division select pin for Bank B. Default = Low. LVCMOS/LVTTL interface levels.
2
VCO_SEL
Input
Pullup
VCO select pin. When Low, the PLL is bypassed and the crystal reference or
TEST_CLK (depending on XTAL_SEL setting) are passed directly to the output
dividers. Has an internal pullup resistor so the PLL is not bypassed by default.
LVCMOS/LVTTL interface levels.
3
MR
Input
Pulldown
Active HIGH Master Reset. When logic HIGH, the internal dividers are reset
causing the true outputs Qx to go low and the inverted outputs nQx to go high.
When logic LOW, the internal dividers and the outputs are enabled. Has an internal
pulldown resistor so the power-up default state of outputs and dividers are enabled.
LVCMOS/LVTTL interface levels.
4VCCO_A
Power
Output supply pin for Bank A outputs.
5, 6
QA0, nQA0
Output
Differential output pair. LVPECL interface levels.
7
OEB
Input
Pullup
Output enable Bank B. Active High output enable. When logic HIGH, the output pair
on Bank B is enabled. When logic LOW, the output pair drives differential Low
(QB0 = Low, nQB0 = High). Has an internal pullup resistor so the default power-up
state of outputs are enabled. LVCMOS/LVTTL interface levels.
8
OEA
Input
Pullup
Output enable Bank A. Active High output enable. When logic HIGH, the 2 output
pairs on Bank A are enabled. When logic LOW, the output pair drives differential
Low (QA0 = Low, nQA0 = High). Has an internal pullup resistor so the default
power-up state of outputs are enabled. LVCMOS/LVTTL interface levels.
9
FB_DIV
Input
Pulldown
Feedback divide select. When Low (default), the feedback divider is set for ÷20.
When HIGH, the feedback divider is set for ÷24. LVCMOS/LVTTL interface levels.
10
VCCA
Power
Analog supply pin.
11
VCC
Power
Core supply pin.
12
DIV_SELA0
Input
Pullup
Division select pin for Bank A. Default = HIGH. LVCMOS/LVTTL interface levels.
13
DIV_SELA1
Input
Pulldown
Division select pin for Bank A. Default = Low. LVCMOS/LVTTL interface levels.
14
VEE
Power
Negative supply pin.
15,
16
XTAL_OUT,
XTAL_IN
Input
Parallel resonant crystal interface. XTAL_OUT is the output, XTAL_IN is the input.
XTAL_IN is also the overdrive pin if you want to overdrive the crystal circuit with a
single-ended reference clock.
17
TEST_CLK
Input
Pulldown
Single-ended reference clock input. Has an internal pulldown resistor to pull to low
state by default. Can leave floating if using the crystal interface.
LVCMOS/LVTTL interface levels.
18
XTAL_SEL
Input
Pullup
Crystal select pin. Selects between the single-ended TEST_CLK or crystal
interface. Has an internal pullup resistor so the crystal interface is selected by
default. LVCMOS/LVTTL interface levels.
19, 20
nQB1, QB1
Output
Differential output pair. LVPECL interface levels.
21, 22
nQB01, QB0
Output
Differential output pair. LVPECL interface levels.
23
VCCO_B
Power
Output supply pin for Bank B outputs.
24
DIV_SELB1
Input
Pullup
Division select pin for Bank B. Default = High. LVCMOS/LVTTL interface levels.
相关PDF资料 |
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| ICS843004AG-01LFT | 156.25 MHz, OTHER CLOCK GENERATOR, PDSO24 |
| ICS843004AG-02LFT | 637.5 MHz, OTHER CLOCK GENERATOR, PDSO24 |
| ICS843004AG-02LF | 680 MHz, OTHER CLOCK GENERATOR, PDSO24 |
| ICS843004AGI-01 | 170 MHz, OTHER CLOCK GENERATOR, PDSO24 |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ICS843003AGLFT | 功能描述:IC SYNTHESIZER LVPECL 24-TSSOP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:HiPerClockS™, FemtoClock™ 标准包装:1,000 系列:- 类型:时钟/频率合成器，扇出分配 PLL:- 输入:- 输出:- 电路数:- 比率 - 输入:输出:- 差分 - 输入:输出:- 频率 - 最大:- 除法器/乘法器:- 电源电压:- 工作温度:- 安装类型:表面贴装 封装/外壳:56-VFQFN 裸露焊盘 供应商设备封装:56-VFQFP-EP（8x8） 包装:带卷 (TR) 其它名称:844S012AKI-01LFT |
| ICS843003AGT | 制造商:ICS 制造商全称:ICS 功能描述:FEMTOCLOCKS CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER |
| ICS843003AI01 | 制造商:ICS 制造商全称:ICS 功能描述:FEMTOCLOCKS-TM CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER |
| ICS843003I-01 | 制造商:ICS 制造商全称:ICS 功能描述:FEMTOCLOCKS-TM CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER |
| ICS843003I-09 | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:FEMTOCLOCKS? CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER |
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