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参数资料
| 型号： | ICS8430AYI-61LF |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 2/20页 |
| 文件大小： | 0K |
| 描述： | IC SYNTHESIZER LVPECL 32-LQFP |
| 标准包装： | 1 |
| 系列： | HiPerClockS™ |
| 类型： | 频率合成器 |
| PLL： | 带旁路 |
| 输入： | 晶体 |
| 输出： | LVPECL |
| 电路数： | 1 |
| 比率 - 输入:输出： | 1:2 |
| 差分 - 输入:输出： | 无/是 |
| 频率 - 最大： | 500MHz |
| 除法器/乘法器： | 是/无 |
| 电源电压： | 3.135 V ~ 3.465 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-LQFP |
| 供应商设备封装： | 32-TQFP（7x7） |
| 包装： | 标准包装 |
| 其它名称： | 800-1924-6 |
8430AYI-61
www.icst.com/products/hiperclocks.html
REV. C JUNE 2, 2006
10
Integrated
Circuit
Systems, Inc.
ICS8430I-61
500MHZ, CRYSTAL-TO-3.3V, 2.5V DIFFERENTIAL
LVPECL FREQUENCY SYNTHESIZER
INPUTS:
CRYSTAL INPUT:
For applications not requiring the use of the crystal oscillator
input, both XTAL_IN and XTAL_OUT can be left floating.
Though not required, but for additional protection, a 1k
Ω
resistor can be tied from XTAL_IN to ground.
TEST_CLK INPUT:
For applications not requiring the use of the test clock, it can
be left floating. Though not required, but for additional
protection, a 1k
Ω resistor can be tied from the TEST_CLK to
ground.
LVCMOS CONTROL PINS:
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1k
Ω resistor can be used.
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
OUTPUTS:
TEST OUTPUT:
The unused TEST output can be left floating. There should
be no trace attached.
LVPECL OUTPUT
All unused LVPECL outputs can be left floating. We
recommend that there is no trace attached. Both sides of the
differential output pair should either be left floating or
terminated.
LVCMOS TO XTAL INTERFACE
The XTAL_IN input can accept a single-ended LVCMOS signal
through an AC coupling capacitor. A general interface diagram
is shown in Figure 4. The XTAL_OUT pin can be left floating.
The input edge rate can be as slow as 10ns. For LVCMOS
inputs, it is recommended that the amplitude be reduced from
full swing to half swing in order to prevent signal interference
with the power rail and to reduce noise. This configuration
requires that the output impedance of the driver (Ro) plus the
FIGURE 4. GENERAL DIAGRAM FOR LVCMOS DRIVER TO XTAL INPUT INTERFACE
series resistance (Rs) equals the transmission line
impedance. In addition, matched termination at the crystal
input will attenuate the signal in half. This can be done in one
of two ways. First, R1 and R2 in parallel should equal the
transmission line impedance. For most 50
Ω applications, R1
and R2 can be 100
Ω. This can also be accomplished by
removing R1 and making R2 50
Ω.
R2
Zo = 50
VDD
Ro
Zo = Ro + Rs
R1
VDD
XTAL_IN
XTAL_OUT
.1uf
Rs
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ICS8430AYI-61LFT | 功能描述:IC SYNTHESIZER LVPECL 32-LQFP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:* 标准包装:1,000 系列:- 类型:时钟/频率合成器，扇出分配 PLL:- 输入:- 输出:- 电路数:- 比率 - 输入:输出:- 差分 - 输入:输出:- 频率 - 最大:- 除法器/乘法器:- 电源电压:- 工作温度:- 安装类型:表面贴装 封装/外壳:56-VFQFN 裸露焊盘 供应商设备封装:56-VFQFP-EP（8x8） 包装:带卷 (TR) 其它名称:844S012AKI-01LFT |
| ICS8430AYI-61T | 制造商:ICS 制造商全称:ICS 功能描述:500MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER |
| ICS8430BI-71L | 制造商:ICS 制造商全称:ICS 功能描述:700MHZ, LOW JITTER, CRYSTAL INTERFACE / LVCMOS-TO-3.3V LVPECL FREQUENCY SYNTHESIZER |
| ICS8430BY-71 | 制造商:ICS 制造商全称:ICS 功能描述:700MHZ, LOW JITTER, CRYSTAL INTERFACE / LVCMOS-TO-3.3V LVPECL FREQUENCY SYNTHESIZER |
| ICS8430BY71L | 制造商:ICS 制造商全称:ICS 功能描述:700MHZ, LOW JITTER, CRYSTAL INTERFACE / LVCMOS-TO-3.3V LVPECL FREQUENCY SYNTHESIZER |
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