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参数资料
| 型号： | ICS8430BYI-71 |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 700 MHz, OTHER CLOCK GENERATOR, PQFP32 |
| 封装： | 7 X 7 MM, 1.40 MM HEIGHT, MS-026BBA, LQFP-32 |
| 文件页数： | 16/16页 |
| 文件大小： | 167K |
| 代理商： | ICS8430BYI-71 |
8430BYI-71
www.icst.com/products/hiperclocks.html
REV. A FEBRUARY 17, 2006
9
Integrated
Circuit
Systems, Inc.
ICS8430BI-71
700MHZ, LOW JITTER, CRYSTAL INTERFACE/
LVCMOS-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
PRELIMINARY
V
CC - 2V
50
Ω
50
Ω
RTT
Z
o = 50Ω
Z
o = 50Ω
FOUT
FIN
RTT =
Z
o
1
((V
OH + VOL) / (VCC – 2)) – 2
3.3V
125
Ω
125
Ω
84
Ω
84
Ω
Z
o = 50Ω
Z
o = 50Ω
FOUT
FIN
The clock layout topology shown below is a typical termina-
tion for LVPECL outputs. The two different layouts mentioned
are recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, termi-
nating resistors (DC current path to ground) or current sources
must be used for functionality. These outputs are designed to
drive 50
Ω transmission lines. Matched impedance tech-
FIGURE 4B. LVPECL OUTPUT TERMINATION
FIGURE 4A. LVPECL OUTPUT TERMINATION
niques should be used to maximize operating frequency
and minimize signal distortion. There are a few simple ter-
mination schemes. Figures 4A and 4B show two different
layouts which are recommended only as guidelines. Other
suitable clock layouts may exist and it would be recom-
mended that the board designers simulate to guarantee
compatibility across all printed circuit and clock component
process variations.
TERMINATION FOR LVPECL OUTPUTS
INPUTS:
CRYSTAL INPUT:
For applications not requiring the use of the crystal oscillator
input, both XTAL_IN and XTAL_OUT can be left floating.
Though not required, but for additional protection, a 1k
Ω
resistor can be tied from XTAL_IN to ground.
TEST_CLK INPUT:
For applications not requiring the use of the test clock, it can
be left floating. Though not required, but for additional
protection, a 1k
Ω resistor can be tied from the TEST_CLK to
ground.
LVCMOS CONTROL PINS:
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1k
Ω resistor can be used.
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
OUTPUTS:
LVPECL OUTPUT
All unused LVPECL outputs can be left floating. We
recommend that there is no trace attached. Both sides of the
differential output pair should either be left floating or
terminated.
相关PDF资料 |
PDF描述 |
|---|---|
| ICS8430BYI-71T | 700 MHz, OTHER CLOCK GENERATOR, PQFP32 |
| ICS8430DY-01T | 500 MHz, OTHER CLOCK GENERATOR, PQFP32 |
| ICS8430DY-111LF | 8430 SERIES, PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| ICS8430DY-111T | 8430 SERIES, PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| ICS8430DY-111LFT | 8430 SERIES, PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ICS8430BYI-71LF | 功能描述:IC SYNTHESIZER DUAL 32-LQFP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:HiPerClockS™ 标准包装:2,000 系列:- 类型:PLL 频率合成器 PLL:是 输入:晶体 输出:时钟 电路数:1 比率 - 输入:输出:1:1 差分 - 输入:输出:无/无 频率 - 最大:1GHz 除法器/乘法器:是/无 电源电压:4.5 V ~ 5.5 V 工作温度:-20°C ~ 85°C 安装类型:表面贴装 封装/外壳:16-LSSOP（0.175"，4.40mm 宽） 供应商设备封装:16-SSOP 包装:带卷 (TR) 其它名称:NJW1504V-TE1-NDNJW1504V-TE1TR |
| ICS8430BYI-71LFT | 功能描述:IC SYNTHESIZER DUAL 32-LQFP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:HiPerClockS™ 标准包装:1,000 系列:- 类型:时钟/频率合成器，扇出分配 PLL:- 输入:- 输出:- 电路数:- 比率 - 输入:输出:- 差分 - 输入:输出:- 频率 - 最大:- 除法器/乘法器:- 电源电压:- 工作温度:- 安装类型:表面贴装 封装/外壳:56-VFQFN 裸露焊盘 供应商设备封装:56-VFQFP-EP（8x8） 包装:带卷 (TR) 其它名称:844S012AKI-01LFT |
| ICS8430BYI-71T | 制造商:ICS 制造商全称:ICS 功能描述:700MHZ, LOW JITTER, CRYSTAL INTERFACE / LVCMOS-TO-3.3V LVPECL FREQUENCY SYNTHESIZER |
| ICS8430CY-11T | 制造商:ICS 制造商全称:ICS 功能描述:700MHZ/350MHZ, LOW PHASE NOISE, CRYSTAL-TO- 3.3V LVPECL FREQUENCY SYNTHESIZER |
| ICS8430DY-111 | 制造商:ICS 制造商全称:ICS 功能描述:700MHZ, LOW JITTER DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER |
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