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| 型号： | ICS8430DY-111LF |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟及定时 |
| 英文描述： | 8430 SERIES, PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| 封装： | 7 X 7 MM, 1.40 MM HEIGHT, ROHS COMPLIANT, MS-026BBA, LQFP-32 |
| 文件页数： | 11/18页 |
| 文件大小： | 350K |
| 代理商： | ICS8430DY-111LF |
IDT / ICS 3.3V LVPECL FREQUENCY SYNTHESIZER
2
ICS8430DY-111 REV. F JANUARY 29, 2007
ICS8430-111
700MHZ, LOW JITTER, DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
PRELIMINARY
The M value and the required values of M0 through M8 are
shown in Table 3B, Programmable VCO Frequency Function
Table. Valid M values for which the PLL will achieve lock are
defined as 125
≤ M ≤ 350. The frequency out is defined as
follows:
Serial operation occurs when nP_LOAD is HIGH and S_LOAD
is LOW. The shift register is loaded by sampling the S_DATA
bits with the rising edge of S_CLOCK. The contents of the shift
register are loaded into the M divider and N output divider when
S_LOAD transitions from LOW-to-HIGH. The M divide and N
output divide values are latched on the HIGH-to-LOW transi-
tion of S_LOAD. If S_LOAD is held HIGH, data at the S_DATA
input is passed directly to the M divider and N output divider on
each rising edge of S_CLOCK. The serial mode can be used to
program the M and N bits and test bits T1 and T0. The internal
registers T0 and T1 determine the state of the TEST output as
follows:
Time
SERIAL LOADING
PARALLEL LOADING
t
S
t
H
t
S
t
H
t
S
M, N
FUNCTIONAL DESCRIPTION
The ICS8430-111 features a fully integrated PLL and there-
fore requires no external components for setting the loop
bandwidth. A differential clock input is used as the input to the
on-chip oscillator. The output of the oscillator is divided by 16
prior to the phase detector. A16MHz clock input provides a
1MHz reference frequency. The VCO of the PLL operates over
a range of 200 to 700MHz. The output of the M divider is also
applied to the phase detector.
The phase detector and the M divider force the VCO output
frequency to be 2M times the reference frequency by adjusting
the VCO control voltage. Note that for some values of M (either
too high or too low), the PLL will not achieve lock. The output
of the VCO is scaled by a divider prior to being sent to each of
the LVPECL output buffers. The divider provides a 50% output
duty cycle.
The programmable features of the ICS8430-111 support two
input modes to program the M divider and N output divider.
The two input operational modes are parallel and serial. Fig-
ure 1 shows the timing diagram for each mode. In parallel mode
the nP_LOAD input is LOW. The data on inputs M0 through
M8 and N0 through N1 is passed directly to the M divider and
N output divider. On the LOW-to-HIGH transition of the
nP_LOAD input, the data is latched and the M divider remains
loaded until the next LOW transition on nP_LOAD or until a
serial event occurs. The TEST output is Mode 000 (shift regis-
ter out) when operating in the parallel input mode. The rela-
tionship between the VCO frequency, the crystal frequency
and the M divider is defined as follows:
T1
T0
TEST Output
00
LOW
0
1
S_Data, Shift Register Input
1
0
Output of M divider
1
CMOS Fout
FIGURE 1. PARALLEL & SERIAL LOAD OPERATIONS
*NOTE: The NULL timing slot must be observed.
S_CLOCK
S_DATA
S_LOAD
nP_LOAD
M0:M8, N0:N1
nP_LOAD
S_LOAD
16
2M
fVCO =
fxtal x
N
fout =
fVCO
=
16
2M
fxtal x
N
相关PDF资料 |
PDF描述 |
|---|---|
| ICS8430DY-111T | 8430 SERIES, PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| ICS8430DY-111LFT | 8430 SERIES, PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| ICS8430DY-111T | 8430 SERIES, PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| ICS8430DY-11LF | 700 MHz, OTHER CLOCK GENERATOR, PQFP32 |
| ICS8430DYI-01T | 500 MHz, OTHER CLOCK GENERATOR, PQFP32 |
相关代理商/技术参数 |
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| ICS8430DY-111LFT | 功能描述:IC SYNTHESIZER DUAL 32-LQFP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:HiPerClockS™ 标准包装:1,000 系列:- 类型:时钟/频率合成器，扇出分配 PLL:- 输入:- 输出:- 电路数:- 比率 - 输入:输出:- 差分 - 输入:输出:- 频率 - 最大:- 除法器/乘法器:- 电源电压:- 工作温度:- 安装类型:表面贴装 封装/外壳:56-VFQFN 裸露焊盘 供应商设备封装:56-VFQFP-EP（8x8） 包装:带卷 (TR) 其它名称:844S012AKI-01LFT |
| ICS8430DY-111T | 制造商:ICS 制造商全称:ICS 功能描述:700MHZ, LOW JITTER DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER |
| ICS8430I-61 | 制造商:ICS 制造商全称:ICS 功能描述:500MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER |
| ICS8430I-71B | 制造商:ICS 制造商全称:ICS 功能描述:700MHZ, LOW JITTER, CRYSTAL INTERFACE / LVCMOS-TO-3.3V LVPECL FREQUENCY SYNTHESIZER |
| ICS8430S07AKILF | 功能描述:IC CLK GENERATOR PLL 32VFQFN RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 专用 系列:- 标准包装:1,500 系列:- 类型:时钟缓冲器/驱动器 PLL:是 主要目的:- 输入:- 输出:- 电路数:- 比率 - 输入:输出:- 差分 - 输入:输出:- 频率 - 最大:- 电源电压:3.3V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:28-SSOP（0.209"，5.30mm 宽） 供应商设备封装:28-SSOP 包装:带卷 (TR) 其它名称:93786AFT |
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