参数资料
型号: ICS8430DY-111LF
厂商: INTEGRATED DEVICE TECHNOLOGY INC
元件分类: 时钟及定时
英文描述: 8430 SERIES, PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32
封装: 7 X 7 MM, 1.40 MM HEIGHT, ROHS COMPLIANT, MS-026BBA, LQFP-32
文件页数: 2/18页
文件大小: 350K
代理商: ICS8430DY-111LF
IDT / ICS 3.3V LVPECL FREQUENCY SYNTHESIZER
10
ICS8430DY-111 REV. F JANUARY 29, 2007
ICS8430-111
700MHZ, LOW JITTER, DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
PRELIMINARY
Figure 3 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = V
CC
/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio
FIGURE 3. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
of R1 and R2 might need to be adjusted to position the V_REF in
the center of the input voltage swing. For example, if the input
clock swing is only 2.5V and V
CC
= 3.3V, V_REF should be 1.25V
and R2/R1 = 0.609.
V_REF
R1
1K
C1
0.1u
R2
1K
Single Ended Clock Input
CLK
nCLK
VCC
相关PDF资料
PDF描述
ICS8430DY-111T 8430 SERIES, PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32
ICS8430DY-111LFT 8430 SERIES, PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32
ICS8430DY-111T 8430 SERIES, PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32
ICS8430DY-11LF 700 MHz, OTHER CLOCK GENERATOR, PQFP32
ICS8430DYI-01T 500 MHz, OTHER CLOCK GENERATOR, PQFP32
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