参数资料
型号: ICS8431EM-11
元件分类: 时钟产生/分配
英文描述: 255 MHz, OTHER CLOCK GENERATOR, PDSO28
封装: 7.50 X 18.05 MM, 2.25 MM HEIGHT, MS-013, MO-119, SOIC-28
文件页数: 10/17页
文件大小: 561K
代理商: ICS8431EM-11
8431EM-11
www.icst.com/products/hiperclocks.html
REV. D OCTOBER 21, 2004
2
Integrated
Circuit
Systems, Inc.
ICS8431-11
255MHZ, LOW JITTER, CRYSTAL OSCILLATOR-
TO
-3.3V LVPECL FREQUENCY SYNTHESIZER
The PLL loop divider or M divider is programmed by using
inputs M0 through M8. While the nP_LOAD input is held LOW,
the data present at M0:M8 is transparent to the M divider. On
the LOW-to-HIGH transition of nP_LOAD, the M0:M8 data is
latched into the M divider and any further changes at the
M0:M8 inputs will not be seen by the M divider until the next
LOW transition on nP_LOAD.
The relationship between the VCO frequency, the crystal fre-
quency and the M divider is defined as follows:
The M value and the required values of M0:M8 for programming
the VCO are shown in
Table 3B, Programmable VCO Frequency
Function Table. The frequency out is defined as follows:
For the ICS8431-11, the output divider equals 2. Valid M val-
ues for which the PLL will achieve lock are defined as:
250
≤ M ≤ 510.
FUNCTIONAL DESCRIPTION
The ICS8431-11 features a fully integrated PLL and therefore
requires no external components for setting the loop bandwidth.
A 16MHz series-resonant, fundamental crystal is used as the
input to the on-chip oscillator. The output of the oscillator is di-
vided by 16 prior to the phase detector. With a 16MHz crystal this
provides a 1MHz reference frequency.The VCO of the PLL oper-
ates over a range of 250MHz to 510MHz. The output of the M
divider is also applied to the phase detector.
The phase detector and the M divider force the VCO output
frequency to be M times the reference frequency by adjusting
the VCO control voltage. Note that for some values of M (ei-
ther too high or too low), the PLL will not achieve lock. The
output of the VCO is scaled by a divider prior to being sent to
the LVPECL output buffer. The divider provides a 50% output
duty cycle.
The programmable features of the ICS8431-11 support four
output operational modes and a programmable M divider and
output divider. The four output operational modes are spread
spectrum clocking (SSC), non-spread spectrum clock and
two test modes and are controlled by the SSC_CTL[1:0] pins.
16
M
fVCO =
fxtal x
2
FOUT =
fVCO
=
32
fxtal x M
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