- 您现在的位置：买卖IC网 > PDF目录67690 > ICS84321AYLFT 260 MHz, OTHER CLOCK GENERATOR, PQFP32 PDF资料下载
参数资料
| 型号： | ICS84321AYLFT |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 260 MHz, OTHER CLOCK GENERATOR, PQFP32 |
| 封装： | 7 X 7 MM, 1.40 MM HEIGHT, LEAD FREE, MS-026, LQFP-32 |
| 文件页数： | 11/18页 |
| 文件大小： | 204K |
| 代理商： | ICS84321AYLFT |
84321AY
www.icst.com/products/hiperclocks.html
REV. B JUNE 9, 2005
2
Integrated
Circuit
Systems, Inc.
ICS84321
260MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL
LVPECL FREQUENCY SYNTHESIZER
cific default state that will automatically occur during power-
up. The TEST output is LOW when operating in the parallel
input mode. The relationship between the VCO frequency, the
crystal frequency and the M divider is defined as follows:
The M value and the required values of M0 through M8 are
shown in Table 3B, Programmable VCO Frequency Function
Table. Valid M values for which the PLL will achieve lock for a
25MHz reference are defined as 25
≤ M ≤ 31. The frequency
out is defined as follows:
Serial operation occurs when nP_LOAD is HIGH and S_LOAD
is LOW. The shift register is loaded by sampling the S_DATA
bits with the rising edge of S_CLOCK. The contents of the
shift register are loaded into the M divider and N output di-
vider when S_LOAD transitions from LOW-to-HIGH. The M
divide and N output divide values are latched on the HIGH-to-
LOW transition of S_LOAD. If S_LOAD is held HIGH, data at
the S_DATA input is passed directly to the M divider and N
output divider on each rising edge of S_CLOCK. The serial
mode can be used to program the M and N bits and test bits
T1 and T0. The internal registers T0 and T1 determine the state
of the TEST output as follows:
FUNCTIONAL DESCRIPTION
NOTE: The functional description that follows describes op-
eration using a 25MHz crystal. Valid PLL loop divider values
for different crystal or input frequencies are defined in the In-
put Frequency Characteristics, Table 5, NOTE 1.
The ICS84321 features a fully integrated PLL and therefore
requires no external components for setting the loop band-
width. A fundamental crystal is used as the input to the on-
chip oscillator. The output of the oscillator is fed into the phase
detector. A 25MHz crystal provides a 25MHz phase detector
reference frequency. The VCO of the PLL operates over a
range of 620MHz to 780MHz. The output of the M divider is
also applied to the phase detector.
The phase detector and the M divider force the VCO output fre-
quency to be M times the reference frequency by adjusting the
VCO control voltage. Note that for some values of M (either too
high or too low), the PLL will not achieve lock. The output of the
VCO is scaled by a divider prior to being sent to each of the LVPECL
output buffers. The divider provides a 50% output duty cycle.
The programmable features of the ICS84321 support two in-
put modes to program the M divider and N output divider. The
two input operational modes are parallel and serial. Figure 1
shows the timing diagram for each mode. In parallel mode,
the nP_LOAD input is initially LOW. The data on inputs M0
through M8 and N0 and N1 is passed directly to the M divider
and N output divider. On the LOW-to-HIGH transition of the
nP_LOAD input, the data is latched and the M divider remains
loaded until the next LOW transition on nP_LOAD or until a
serial event occurs. As a result, the M and N bits can be
hardwired to set the M divider and N output divider to a spe-
fVCO = fxtal x M
T1
T0
TEST Output
0
LOW
0
1
S_DATA, Shift Register Input
1
0
Output of M divider
1
CMOS Fout
FIGURE 1. PARALLEL & SERIAL LOAD OPERATIONS
*NOTE: The NULL timing slot must be observed.
Time
SERIAL LOADING
PARALLEL LOADING
t
S
t
H
t
S
t
H
t
S
M, N
T1
T0
*NULL
N 1
N 0
M8
M7
M6
M5
M4
M3
M2
M1
M 0
S_CLOCK
S_DATA
S_LOAD
nP_LOAD
M0:M8, N0:N1
nP_LOAD
S_LOAD
FOUT = fVCO = fxtal x M
N
相关PDF资料 |
PDF描述 |
|---|---|
| ICS843246AMIT | 333.33 MHz, OTHER CLOCK GENERATOR, PDSO24 |
| ICS843246AMLFT | 333.33 MHz, OTHER CLOCK GENERATOR, PDSO24 |
| ICS843246AGT | 333.33 MHz, OTHER CLOCK GENERATOR, PDSO24 |
| ICS843246AMLF | 333.33 MHz, OTHER CLOCK GENERATOR, PDSO24 |
| ICS84324AMLFT | 125 MHz, OTHER CLOCK GENERATOR, PDSO24 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ICS84321AYT | 制造商:ICS 制造商全称:ICS 功能描述:260MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER |
| ICS84321I | 制造商:ICS 制造商全称:ICS 功能描述:260MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER |
| ICS84324 | 制造商:ICS 制造商全称:ICS 功能描述:CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER WITH FANOUT BUFFER |
| ICS843241I-04 | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:FEMTOCLOCKSa?￠ CRYSTAL-TO-3.3V, 2.5V LVPECL CLOCK GENERATOR |
| ICS843242 | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:FEMTOCLOCKS⑩ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER |
发布紧急采购，3分钟左右您将得到回复。