参数资料
型号: ICS854210CYT
厂商: INTEGRATED DEVICE TECHNOLOGY INC
元件分类: 时钟及定时
英文描述: 854210 SERIES, LOW SKEW CLOCK DRIVER, 5 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32
封装: 7 X 7 MM, 1.40 MM HEIGHT, MS-026BBA, LQFP-32
文件页数: 9/11页
文件大小: 693K
代理商: ICS854210CYT
IDT / ICS LVDS FANOUT BUFFER
7
ICS854210CY REV B OCTOBER 31, 2006
ICS854210
LOW SKEW, DUAL, 1-TO-5 DIFFERENTIAL-TO-LVDS FANOUT BUFFER
PRELIMINARY
LVPECL CLOCK INPUT INTERFACE
The PCLK /nPCLK accepts LVPECL, CML, SSTL and other
differential signals. Both V
SWING
and V
OH must
meet the V
PP and
V
CMR
input requirements.
Figures 2A to 2F show interface
examples for the HiPerClockS PCLK/nPCLK input driven by
the most common driver types. The input interfaces suggested
here are examples only. If the driver is from another vendor,
use their termination recommendation. Please consult with the
vendor of the driver component to confirm the driver termination
requirements.
FIGURE 2A. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY AN
OPEN COLLECTOR CML DRIVER
FIGURE 2B. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY A
BUILT-IN PULLUP CML DRIVER
FIGURE 2C. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY A
3.3V LVPECL DRIVER
PCLK/nPCLK
2.5V
Zo = 60 Ohm
SSTL
HiPerClockS
PCLK
nPCLK
R2
120
3.3V
R3
120
Zo = 60 Ohm
R1
120
R4
120
2.5V
HiPerClockS
PCLK
nPCLK
PCLK/nPCLK
3.3V
R2
50
R1
50
3.3V
Zo = 50 Ohm
CML
3.3V
Zo = 50 Ohm
3.3V
HiPerClockS
PCLK
nPCLK
R2
84
R3
125
Input
Zo = 50 Ohm
R4
125
R1
84
LVPECL
3.3V
Zo = 50 Ohm
FIGURE 2D. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY AN
SSTL DRIVER
3.3V
CML Built-In Pullup
R1
100
PCLK
nPCLK
HiPerClockS
PCLK/nPCLK
Zo = 50 Ohm
LVDS DRIVER TERMINATION
A general LVDS interface is shown in
Figure 3. In a 100
differential transmission line environment, LVDS drivers require
a matched load termination of 100
across near the receiver
100 Ohm Differiential Transmission Line
R1
100
3.3V
+
-
LVDS_Driv er
3.3V
FIGURE 3. TYPICAL LVDS DRIVER TERMINATION
input. For a multiple LVDS outputs buffer, if only partial outputs
are used, it is recommended to terminate the unused outputs.
相关PDF资料
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ICS8543BGILF LOW SKEW CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO20
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