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参数资料
| 型号： | ICS854S013IT |
| 元件分类： | 时钟及定时 |
| 英文描述： | 854S SERIES, LOW SKEW CLOCK DRIVER, 3 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO20 |
| 封装： | 6.50 X 4.40 MM, 0.92 MM HEIGHT, MS-153, TSSOP-20 |
| 文件页数： | 13/14页 |
| 文件大小： | 407K |
| 代理商： | ICS854S013IT |
854S013AGI
www.icst.com/products/hiperclocks.html
REV. A JUNE 16, 2006
8
Integrated
Circuit
Systems, Inc.
ICS854S013I
LOW SKEW, DUAL, 1-TO-3
DIFFERENTIAL-TO-LVDS FANOUT BUFFER
PRELIMINARY
APPLICATION INFORMATION
INPUTS:
PCLK/nPCLK INPUT:
For applications not requiring the use of a differential input,
both the PCLK and nPCLK pins can be left floating. Though
not required, but for additional protection, a 1k
resistor can
be tied from PCLK to ground.
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
OUTPUTS:
LVDS OUTPUT
All unused LVDS output pairs can be either left floating or
terminated with 100
across. If they are left floating, there
should be no trace attached.
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 1 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = V
CC/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The
FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
ratio of R1 and R2 might need to be adjusted to position the
V_REF in the center of the input voltage swing. For example, if
the input clock swing is only 2.5V and V
CC= 3.3V, V_REF should
be 1.25V and R2/R1 = 0.609.
VCC
R2
1K
V_REF
C1
0.1u
R1
1K
Single Ended Clock Input
PCLK
nPCLK
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