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参数资料
| 型号： | ICS854S013IT |
| 元件分类： | 时钟及定时 |
| 英文描述： | 854S SERIES, LOW SKEW CLOCK DRIVER, 3 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO20 |
| 封装： | 6.50 X 4.40 MM, 0.92 MM HEIGHT, MS-153, TSSOP-20 |
| 文件页数： | 14/14页 |
| 文件大小： | 407K |
| 代理商： | ICS854S013IT |
854S013AGI
www.icst.com/products/hiperclocks.html
REV. A JUNE 16, 2006
9
Integrated
Circuit
Systems, Inc.
ICS854S013I
LOW SKEW, DUAL, 1-TO-3
DIFFERENTIAL-TO-LVDS FANOUT BUFFER
PRELIMINARY
LVPECL CLOCK INPUT INTERFACE
The PCLKx /nPCLKx accepts LVPECL, CML, SSTL and other
differential signals. Both V
SWING and VOH must meet the VPP
and V
CMR input requirements.
Figures 2A to 2E show inter-
face examples for the HiPerClockS PCLKx/nPCLKx input
driven by the most common driver types. The input inter-
faces suggested here are examples only. If the driver is
from another vendor, use their termination recommenda-
tion. Please consult with the vendor of the driver compo-
nent to confirm the driver termination requirements.
FIGURE 2A. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY A
CML DRIVER
FIGURE 2B. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY AN
SSTL DRIVER
FIGURE 2C. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY A
3.3V LVPECL DRIVER
FIGURE 2D. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY A
3.3V LVDS DRIVER
HiPerClockS
PCLK
nPCLK
PCLK/nPCLK
3.3V
R2
50
R1
50
3.3V
Zo = 50 Ohm
CML
3.3V
Zo = 50 Ohm
PCLK/nPCLK
2.5V
Zo = 60 Ohm
SSTL
HiPerClockS
PCLK
nPCLK
R2
120
3.3V
R3
120
Zo = 60 Ohm
R1
120
R4
120
2.5V
FIGURE 2E. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY A
3.3V LVPECL DRIVER WITH AC COUPLE
3.3V
R5
100 - 200
3.3V
HiPerClockS
PCLK
nPCLK
R1
125
PCLK/nPCLK
R2
125
R3
84
C1
C2
Zo = 50 Ohm
R4
84
Zo = 50 Ohm
R6
100 - 200
3.3V LVPECL
3.3V
HiPerClockS
PCLK
nPCLK
R2
84
R3
125
Input
Zo = 50 Ohm
R4
125
R1
84
LVPECL
3.3V
Zo = 50 Ohm
C2
R2
1K
R5
100
Zo = 50 Ohm
3.3V
C1
R3
1K
LVDS
R4
1K
HiPerClockS
PCLK
nPCLK
R1
1K
Zo = 50 Ohm
3.3V
PC L K /n PC LK
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