参数资料
型号: ICS86004G-01
厂商: INTEGRATED DEVICE TECHNOLOGY INC
元件分类: 时钟及定时
英文描述: 86004 SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16
封装: 4.40 X 5.0 MM, 0.92 MM HEIGHT, MO-153, TSSOP-16
文件页数: 1/13页
文件大小: 604K
代理商: ICS86004G-01
62.5MHZ TO 250MHZ, 1:4 LVCMOS/
LVTTL ZERO DELAY CLOCK BUFFER
ICS86004-01
IDT / ICS LVCMOS ZERO DELAY CLOCK BUFFER
1
ICS86004BG-01 REV C NOVEMBER 30, 2006
GENERAL DESCRIPTION
The ICS86004-01 is a high performance 1-to-4
LVCMOS/LVTTL Clock Buffer and a member of
the HiPerClockS family of High Performance
Clock Solutions from IDT. The ICS86004-01 has a
fully integrated PLL and can be configured as zero
delay buffer and has an input and output frequency range of
62.5MHz to 250MHz. The exter nal feedback allows the
device to achieve “zero delay” between the input clock and the
output clocks. The PLL_SEL pin can be used to bypass the
PLL for system test and debug purposes. In bypass mode, the
reference clock is routed around the PLL and into the
internal output divider.
FEATURES
Four LVCMOS/LVTTL outputs, 7
typical output impedance
Single LVCMOS/LVTTL clock input
CLK accepts the following input levels: LVCMOS or LVTTL
Output frequency range: 62.5MHz to 250MHz
Input frequency range: 62.5MHz to 250MHz
External feedback for “zero delay” clock regeneration
with configurable frequencies
Fully integrated PLL
Cycle-to-cycle jitter, (F_SEL = 1): 45ps (maximum)
Output skew: 60ps (maximum)
Supply Voltage Modes:
(Core/Output)
3.3V/3.3V
3.3V/2.5V
2.5V/2.5V
5V tolerant input
-40°C to 70°C ambient operating temperature
Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
HiPerClockS
ICS
BLOCK DIAGRAM
PIN ASSIGNMENT
PLL_SEL
CLK
FB_IN
MR
F_SEL
Q0
Q1
Q2
Q3
PLL
1:1
÷8
0
1
Q1
GND
Q0
F_SEL
VDD
CLK
GND
VDDA
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VDDO
Q2
GND
Q3
VDDO
MR
FB_IN
PLL_SEL
ICS86004-01
16-Lead TSSOP
4.4mm x 5.0mm x 0.92mm package body
G Package
Top View
CONTROL INPUT FUNCTION TABLE
t
u
p
n
I
t
u
p
t
u
O
/
t
u
p
n
I
)
z
H
M
(
e
g
n
a
R
y
c
n
e
u
q
e
r
F
L
E
S
_
Fm
u
m
i
n
i
Mm
u
m
i
x
a
M
05
2
10
5
2
15
.
2
65
2
1
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