参数资料
型号: ICS87002AG-02LF
元件分类: 时钟及定时
英文描述: 87002 SERIES, PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO20
封装: 6.50 X 4.40 MM, 0.92 MM HEIGHT, ROHS COMPLIANT, PLASTIC, MO-153, TSS0P20
文件页数: 13/13页
文件大小: 385K
代理商: ICS87002AG-02LF
87002AG-02
www.icst.com/products/hiperclocks.html
REV. A OCTOBER 5, 2005
9
Integrated
Circuit
Systems, Inc.
ICS87002-02
1:2, DIFFERENTIAL-TO-LVCMOS/LVTTL
ZERO DELAY CLOCK GENERATOR
APPLICATION INFORMATION
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS87002-02 provides
separate power supplies to isolate any high switching
noise from the outputs to the internal PLL. V
DD, VDDA, and VDDO
should be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required. Figure 1 illustrates how
a 10
Ω resistor along with a 10F and a .01μF bypass
capacitor should be connected to each V
DDA.
POWER SUPPLY FILTERING TECHNIQUES
FIGURE 1. POWER SUPPLY FILTERING
10
Ω
V
DDA
10
μF
.01
μF
3.3V or 2.5V
.01
μF
V
DD
Figure 2 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = V
DD/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio
FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
of R1 and R2 might need to be adjusted to position the V_REF in
the center of the input voltage swing. For example, if the input
clock swing is only 2.5V and V
DD = 3.3V, V_REF should be 1.25V
and R2/R1 = 0.609.
V_REF
R1
1K
C1
0.1u
R2
1K
Single Ended Clock Input
CLK
nCLK
VDD
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