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参数资料
| 型号： | ICS873995AY |
| 元件分类： | 时钟及定时 |
| 英文描述： | 873995 SERIES, PLL BASED CLOCK DRIVER, 6 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP48 |
| 封装： | 7 X 7 MM, 1 MM HEIGHT, MS-026, TQFP-48 |
| 文件页数： | 14/16页 |
| 文件大小： | 239K |
| 代理商： | ICS873995AY |
873995AY
www.icst.com/products/hiperclocks.html
REV. A APRIL 12, 2006
7
Integrated
Circuit
Systems, Inc.
ICS873995
DIFFERENTIAL-TO-3.3V LVPECL
ZERO DELAY/MULTIPLIER/DIVIDER
PRELIMINARY
APPLICATIONS INFORMATION
CLOCK REDUNDANCY AND REFERENCE SELECTION
The ICS873995 accepts two differential input clocks, CLK0/
nCLK0 and CLK1/nCLK1, for the purpose of redundancy. Only
one of these clocks can be selected at any given time for use
as the reference. One clock will be defined during the initializa-
tion process as the initial, or primary clock, while the remaining
clock is the redundant or secondary clock. During the initializa-
tion process, input signal SEL_CLK determines which input clock
will be used as the initial clock. When SEL_CLK is driven HIGH,
the initial clock to be used as the reference is CLK1/nCLK1,
otherwise an internal pulldown pulls this input LOW so that
the initial clock input is CLK0/nCLK0. The output signal
CLK_SELECTED indicates which clock input is being used
as the reference (LOW = CLK0/nCLK0, HIGH = CLK1/nCLK1),
and will initially be at the same level as SEL_CLK.
INITIALIZATION EVENT
An initialization event is required to specify the initial input
clock. In order to run an initialization event, nINIT must transi-
tion from HIGH-to-LOW. Following a HIGH-to-LOW transition
of nINIT, the input clock specified on the SEL_CLK input will
be set as the initial input clock. In addition, both input-bad
flags (INP0BAD and INP1BAD outputs) will be cleared.
FALILURE DETECTION AND ALARM SIGNALING
Within the ICS873995 device, CLK0/nCLK0 and CLK1/nCLK1
are continuously monitored for failures. A failure on either of
these clocks is detected when one of the clock signals is stuck
HIGH or LOW for at least 1 period of the Feedback. Upon de-
tection of a failure, the corresponding input-bad signal,
INP0BAD or INP1BAD, will be set HIGH. The input clocks are
continuously monitored and the input-bad signals will con-
tinue to reflect the real-time status of each input clock.
MANUAL CLOCK SWITCHING
When input signal MAN_OVERRIDE is driven HIGH, the
clock specified by SEL_CLK will always be used as the
reference, even when a clock failure is detected at the
reference. In order to switch between CLK0/nCLK0 and CLK1/
nCLK1 as the reference clock, the level on SEL_CLK must
be driven to the appropriate level. When the level on
SEL_CLK is changed, the selection of the new clock will
take place, and CLK_SELECTED will be updated to indi-
cate which clock is now supplying the reference to the PLL.
DYNAMIC CLOCK SWITCHING
The Dynamic Clock Switching (DCS) process serves as an
automatic safety mechanism to protect the stability of the PLL
when a failure occurs on the reference.
When input signal MAN_OVERRIDE is not driven HIGH, an
internal pulldown pulls it LOW so that DCS is enabled. If DCS
is enabled and a failure occurs on the initial clock, the
ICS873995 device will check the status of the secondary
clock. If the secondary clock is detected as a good input clock,
the ICS873995 will automatically deselect the initial clock as
the reference and multiplex in the secondary clock. When a
successful switch from the initial to secondary clock has
been accomplished, CLK_SELECTED will be updated to
indicate the new reference. If and when the fault on the initial
clock is corrected, the corresponding input bad flag will be
updated to represent this clock as good again. However, the
DCS will not undergo an unneccessary clock switch as long
as the secondary clock remains good. If, at a later time, a fail-
ure occurs on the secondary clock, the ICS873995 will then
switch to the initial clock if it is detected as good. See the
Dynamic Clock Switch State Diagram (Figure X) and the
Dynamic Clock Switch Flowchart (Figure Y) for complete de-
tails on the functionality of the Dynamic Clock Switching circuit.
OUTPUT TRANSITIONING
After a successful manual or DCS initiated clock switch, the
internal PLL of the ICS873995 will begin slewing to phase/
frequency alignment. The PLL will achieve lock to the new
input with minimal phase disturbance at the outputs.
MASTER RESET OPERATION
When input signal nMR is driven LOW, the output clocks are
high impedance and the internal dividers of the ICS873995
are reset. With no signal driving nMR, an internal pullup
pulls nMR HIGH and the output clocks and internal divid-
ers are enabled.
RECOMMENDED POWER-UP SEQUENCE
1. Before star tup, set MAN_OVERRIDE HIGH and set
SEL_CLK to the desired input clock. This will ensure that,
during startup, the PLL will acquire lock using the input clock
specified by SEL_CLK.
2. Once powered-up, and assuming a stable clock free of
failures is present at the clock designated by SEL_CLK, the
PLL will begin to phase/frequency slew as it attempts to
achieve lock with the input reference clock.
3. Drive MAN_OVERRIDE LOW to enable DCS mode.
4. Transition nINIT from HIGH-to-LOW in order to clear both
input-bad flags and to set the initial input clock.
ALTERNATE POWER-UP SEQUENCE
If both input clocks are valid before power up, the part may be
powered-up in DCS mode. However, it cannot be guaranteed
that the PLL will achieve lock with one specific input clock.
1. Before startup, leave MAN_OVERRIDE floating and the
internal pulldown will enable DCS mode.
2. Once powered up, the PLL will begin to phase/frequency
slew as it attempts to achieve lock with one of the input refer-
ence clocks.
3. Transition nINIT from HIGH-to-LOW in order to clear both
input-bad flags and to set the initial input clock.
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相关代理商/技术参数 |
参数描述 |
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