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| 型号： | ICS8745BM-21LF |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟及定时 |
| 英文描述： | 8745 SERIES, PLL BASED CLOCK DRIVER, 1 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO20 |
| 封装： | 7.50 X 12.80 MM, 2.30 MM HEIGHT, ROHS COMPLIANT, MS-013, MO-119, SOIC-20 |
| 文件页数： | 6/19页 |
| 文件大小： | 840K |
| 代理商： | ICS8745BM-21LF |
ICS8745B-21
1:1 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR
IDT / ICS LVDS ZERO DELAY CLOCK GENERATOR
14
ICS8745BM-21REV. C APRIL 17, 2007
The following component footprints are used in this layout
example.
All the resistors and capacitors are size 0603.
Power and Grounding
Place the decoupling capacitors as close as possible to the power
pins. If space allows, placement of the decoupling capacitor on the
component side is preferred. This can reduce unwanted
inductance between the decoupling capacitor and the power pin
caused by the via.
Maximize the power and ground pad sizes and number of vias
capacitors. This can reduce the inductance between the power and
ground planes and the component power and ground pins.
The RC filter consisting of R7, C11, and C16 should be placed as
close to the VDDA pin as possible.
Clock Traces and Termination
Poor signal integrity can degrade the system performance or cause
system failure. In synchronous high-speed digital systems, the
clock signal is less tolerant to poor signal integrity than other
signals. Any ringing on the rising or falling edge or excessive ring
back can cause system failure. The shape of the trace and the
trace delay might be restricted by the available space on the board
and the component location. While routing the traces, the clock
signal traces should be routed first and should be locked prior to
routing other signal traces.
The differential 50Ω output traces should have the same
length.
Avoid sharp angles on the clock trace. Sharp angle turns
cause the characteristic impedance to change on the
transmission lines.
Keep the clock traces on the same layer. Whenever
possible, avoid placing vias on the clock traces.
Placement of vias on the traces can affect the trace
characteristic impedance and hence degrade signal
integrity.
To prevent cross talk, avoid routing other signal traces in
parallel with the clock traces. If running parallel traces is
unavoidable, allow a separation of at least three trace
widths between the differential clock trace and the other
signal trace.
Make sure no other signal traces are routed between the
clock trace pair.
The matching termination resistors should be located as
close to the receiver input pins as possible.
Figure 5B. PCB Board Layout for ICS8745B-21
100 Ohm
Differential
Traces
VDDA
VDD
C2
U1
R7
C16
VDDO
GND
C4
C1
I
CS8745B-21
VIA
C11
相关PDF资料 |
PDF描述 |
|---|---|
| ICS8745BM-21T | 8745 SERIES, PLL BASED CLOCK DRIVER, 1 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO20 |
| ICS8745BMI-21LF | 8745 SERIES, PLL BASED CLOCK DRIVER, 1 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO20 |
| ICS8745BMI-21 | 8745 SERIES, PLL BASED CLOCK DRIVER, 1 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO20 |
| ICS8745BMI-21LF | PLL BASED CLOCK DRIVER, 1 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO20 |
| ICS8745BMI-21 | PLL BASED CLOCK DRIVER, 1 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO20 |
相关代理商/技术参数 |
参数描述 |
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| ICS8745BM-21LFT | 功能描述:IC CLK GEN 1:1 DIFF-LVDS 20-SOIC RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:HiPerClockS™ 标准包装:1,000 系列:- 类型:时钟/频率合成器，扇出分配 PLL:- 输入:- 输出:- 电路数:- 比率 - 输入:输出:- 差分 - 输入:输出:- 频率 - 最大:- 除法器/乘法器:- 电源电压:- 工作温度:- 安装类型:表面贴装 封装/外壳:56-VFQFN 裸露焊盘 供应商设备封装:56-VFQFP-EP（8x8） 包装:带卷 (TR) 其它名称:844S012AKI-01LFT |
| ICS8745BMI-21LF | 功能描述:IC CLK GEN 1:1 DIFF-LVDS 20-SOIC RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:HiPerClockS™ 标准包装:1,000 系列:Precision Edge® 类型:时钟/频率合成器 PLL:无 输入:CML，PECL 输出:CML 电路数:1 比率 - 输入:输出:2:1 差分 - 输入:输出:是/是 频率 - 最大:10.7GHz 除法器/乘法器:无/无 电源电压:2.375 V ~ 3.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:16-VFQFN 裸露焊盘，16-MLF? 供应商设备封装:16-MLF?（3x3） 包装:带卷 (TR) 其它名称:SY58052UMGTRSY58052UMGTR-ND |
| ICS8745BMI-21LFT | 功能描述:IC CLK GEN 1:1 DIFF-LVDS 20-SOIC RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:HiPerClockS™ 标准包装:1,000 系列:- 类型:时钟/频率合成器，扇出分配 PLL:- 输入:- 输出:- 电路数:- 比率 - 输入:输出:- 差分 - 输入:输出:- 频率 - 最大:- 除法器/乘法器:- 电源电压:- 工作温度:- 安装类型:表面贴装 封装/外壳:56-VFQFN 裸露焊盘 供应商设备封装:56-VFQFP-EP（8x8） 包装:带卷 (TR) 其它名称:844S012AKI-01LFT |
| ICS8745BY | 制造商:ICS 功能描述: 制造商:Integrated Device Technology Inc 功能描述: 制造商:Integrated Device Technology Inc 功能描述:8745 SERIES, PLL BASED CLOCK DRIVER, 5 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| ICS8745BYI | 制造商:Integrated Device Technology Inc 功能描述: |
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