参数资料
型号: ICS8745BMI-21
元件分类: 时钟及定时
英文描述: PLL BASED CLOCK DRIVER, 1 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO20
封装: 7.50 X 12.80 MM, 2.30 MM HEIGHT, MO-119, SOIC-20
文件页数: 2/15页
文件大小: 207K
代理商: ICS8745BMI-21
8745BMI-21
www.icst.com/products/hiperclocks.html
REV. B MARCH 17, 2004
10
Integrated
Circuit
Systems, Inc.
ICS8745BI-21
1:1 DIFFERENTIAL-TO-LVDS
ZERO DELAY CLOCK GENERATOR
SEL2
PLL_SEL
RD6
SP
RD4
SP
R4
100
VDD
RU3
1K
SP = Space (i.e. not intstalled)
SEL0
SEL3
RU4
1K
SEL[3:0] = 0101,
Divide by 2
R8
50
RD7
1K
(77.76 MHz)
VDDO
VDD
C1
0.1uF
Bypass capacitors located
near the power pins
RU5
SP
C16
10u
SEL3
VDDO
(U1-7)
Zo = 50 Ohm
VDDA
3.3V PECL Driv er
SEL1
R9
50
VDD=3.3V
VDDO
R10
50
SEL0
Zo = 50 Ohm
RD5
1K
C11
0.01u
(U1-11)
C4
0.1uF
SEL2
(155.52 MHz)
LVDS_input
+
-
Zo = 100 Ohm Dif f erential
R2
100
SEL1
RU7
SP
C2
0.1uF
R7
10
PLL_SEL
U1
ICS8745B-21
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
20
19
18
17
CLK
nCLK
MR
nFB_IN
FB_IN
SEL2
VDDO
nQFB
QFB
GND
VDDO
nQ
Q
GND
SEL3
VDDA
SEL1
SEL0
VDDI
PLL_SEL
RD3
SP
VDD
VDDO=3.3V
RU6
1K
3.3V
LAYOUT GUIDELINE
The schematic of the ICS8745BI-21 layout example is shown in
Figure 5A. The ICS8745BI-21 recommended PCB board layout
for this example is shown in
Figure 5B. This layout example is
used as a general guideline. The layout in the actual system will
depend on the selected component types and the density of the
P.C. board.
FIGURE 5A. ICS8745BI-21 LVDS ZERO DELAY BUFFER SCHEMATIC EXAMPLE
相关PDF资料
PDF描述
ICS8745BYIT 8745 SERIES, PLL BASED CLOCK DRIVER, 5 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32
ICS8745BYI 8745 SERIES, PLL BASED CLOCK DRIVER, 5 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32
ICS874S02AMILF 874S SERIES, PLL BASED CLOCK DRIVER, 1 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO20
ICS874S02AMI 874S SERIES, PLL BASED CLOCK DRIVER, 1 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO20
ICS874S02AMIT 874S SERIES, PLL BASED CLOCK DRIVER, 1 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO20
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