- 您现在的位置：买卖IC网 > PDF目录67703 > ICS874S02BMILF (INTEGRATED DEVICE TECHNOLOGY INC) 874S SERIES, PLL BASED CLOCK DRIVER, 1 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO20 PDF资料下载
参数资料
| 型号： | ICS874S02BMILF |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟及定时 |
| 英文描述： | 874S SERIES, PLL BASED CLOCK DRIVER, 1 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO20 |
| 封装： | 7.50 X 12.80 MM, 2.30 MM HEIGHT, ROHS COMPLIANT, MS-013, MO-119, SOIC-20 |
| 文件页数： | 2/15页 |
| 文件大小： | 786K |
| 代理商： | ICS874S02BMILF |
874S02BMI
10
REV. A JANUARY 21, 2008
ICS874S02I
1:1 DIFFERENTIAL-TO-LVDS
ZERO DELAY CLOCK GENERATOR
PRELIMINARY
LAYOUT GUIDELINE
The schematic of the ICS874S02I layout example is shown in
Figure 5A. The ICS874S02I recommended PCB board layout
for this example is shown in
Figure 5B. This layout example is
used as a general guideline. The layout in the actual system will
depend on the selected component types and the density of
the P.C. board.
FIGURE 5A. ICS874S02I LVDS ZERO DELAY BUFFER SCHEMATIC EXAMPLE
SEL2
PLL_SEL
RD6
SP
RD4
SP
R4
100
VDD
RU3
1K
SP = Space (i.e. not intstalled)
SEL0
SEL3
RU4
1K
SEL[3:0] = 0101,
Divide by 2
R8
50
RD7
1K
(77.76 MHz)
VDDO
VDD
C1
0.1uF
Bypass capacitors located
near the power pins
RU5
SP
C16
10u
SEL3
VDDO
(U1-7)
Zo = 50 Ohm
VDDA
3.3V PECL Driv er
SEL1
R9
50
VDD=3.3V
VDDO
R10
50
SEL0
Zo = 50 Ohm
RD5
1K
C11
0.01u
(U1-11)
C4
0.1uF
SEL2
(155.52 MHz)
LVDS_input
+
-
Zo = 100 Ohm Dif f erential
R2
100
SEL1
RU7
SP
C2
0.1uF
R7
10
PLL_SEL
U1
ICS8745B-21
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
20
19
18
17
CLK
nCLK
MR
nFB_IN
FB_IN
SEL2
VDDO
nQFB
QFB
GND
VDDO
nQ
Q
GND
SEL3
VDDA
SEL1
SEL0
VDDI
PLL_SEL
RD3
SP
VDD
VDDO=3.3V
RU6
1K
3.3V
LVDS DRIVER TERMINATION
A general LVDS interface is shown in
Figure 4. In a 100
differential transmission line environment, LVDS drivers re-
quire a matched load termination of 100
across near the
FIGURE 4. TYPICAL LVDS DRIVER TERMINATION
receiver input. For a multiple LVDS outputs buffer, if only par-
tial outputs are used, it is recommended to terminate the un-
used outputs.
100 Ohm Differiential Transmission Line
R1
100
3.3V
+
-
LVDS_Driv er
3.3V
相关PDF资料 |
PDF描述 |
|---|---|
| ICS874S02BMI | 874S SERIES, PLL BASED CLOCK DRIVER, 1 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO20 |
| ICS8752CYI | 8752 SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| ICS8752CYLF | 8752 SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| ICS8761CYILF | 166.67 MHz, PROC SPECIFIC CLOCK GENERATOR, PQFP64 |
| ICS87931BYI | 87931 SERIES, PLL BASED CLOCK DRIVER, 6 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ICS874S02BMILFT | 功能描述:IC CLK GEN 1:1 DIFF ZD 20SOIC RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:HiPerClockS™ 标准包装:1,000 系列:- 类型:时钟/频率合成器，扇出分配 PLL:- 输入:- 输出:- 电路数:- 比率 - 输入:输出:- 差分 - 输入:输出:- 频率 - 最大:- 除法器/乘法器:- 电源电压:- 工作温度:- 安装类型:表面贴装 封装/外壳:56-VFQFN 裸露焊盘 供应商设备封装:56-VFQFP-EP（8x8） 包装:带卷 (TR) 其它名称:844S012AKI-01LFT |
| ICS874S02BMIT | 制造商:Integrated Device Technology Inc 功能描述:IC CLK GENERATOR ZDB 20SOIC |
| ICS874S336AGLF | 功能描述:IC CLOCK MULTIPLIER LVDS 20TSSOP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:HiPerClockS™ 标准包装:27 系列:Precision Edge® 类型:频率合成器 PLL:是 输入:PECL，晶体 输出:PECL 电路数:1 比率 - 输入:输出:1:1 差分 - 输入:输出:无/是 频率 - 最大:800MHz 除法器/乘法器:是/无 电源电压:3.135 V ~ 5.25 V 工作温度:0°C ~ 85°C 安装类型:表面贴装 封装/外壳:28-SOIC（0.295"，7.50mm 宽） 供应商设备封装:28-SOIC 包装:管件 |
| ICS874S336AGLFT | 功能描述:IC CLOCK MULTIPLIER LVDS 20TSSOP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:HiPerClockS™ 标准包装:27 系列:Precision Edge® 类型:频率合成器 PLL:是 输入:PECL，晶体 输出:PECL 电路数:1 比率 - 输入:输出:1:1 差分 - 输入:输出:无/是 频率 - 最大:800MHz 除法器/乘法器:是/无 电源电压:3.135 V ~ 5.25 V 工作温度:0°C ~ 85°C 安装类型:表面贴装 封装/外壳:28-SOIC（0.295"，7.50mm 宽） 供应商设备封装:28-SOIC 包装:管件 |
| ICS8752CY | 制造商:INT_CIR_SYS 功能描述: |
发布紧急采购，3分钟左右您将得到回复。