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参数资料
| 型号： | ICS879893BYI |
| 元件分类： | 时钟及定时 |
| 英文描述： | 879893 SERIES, PLL BASED CLOCK DRIVER, 12 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP48 |
| 封装： | 7 X 7 MM, 1.40 MM HEIGHT, MS-026, LQFP-48 |
| 文件页数： | 3/16页 |
| 文件大小： | 233K |
| 代理商： | ICS879893BYI |
Integrated
Circuit
Systems, Inc.
879893BYI
www.icst.com/products/hiperclocks.html
REV. A JULY 12, 2005
11
ICS879893BI
LOW SKEW, 1-TO-12 (IDCS)
LVCMOS/LVTTL CLOCK GENERATOR
PRELIMINARY
APPLICATIONS INFORMATION
CLOCK REDUNDANCY AND REFERENCE SELECTION
The ICS879893BI accepts two LVCMOS/LVTTL single ended
input clocks, CLK0 and CLK1, for the purpose of redundancy.
Only one of these clocks can be selected at any given time for
use as the reference. The clock that is used by default as the
reference is referred to as the primary clock, while the remain-
ing clock is the redundant or secondary clock. Input signal
REF_SEL determines which input is to be used as the primary
and which is to be used as the secondary. When REF_SEL is
driven HIGH, the primary clock input is CLK1, otherwise an in-
ternal pull down pulls this input LOW so that the primary clock
input is CLK0. The output signal CLK_IND indicates which clock
input is being used as the reference (LOW = CLK0, HIGH =
CLK1), and will initially be at the same level as REF_SEL.
FAILURE DETECTION AND ALARM SIGNALING
Within the ICS879893BI device, CLK0 and CLK are continuously
monitored for failures. A failure on either of these clocks is de-
tected when one of the clock signals is stuck HIGH or LOW for
at least 1 period. Upon detection of a failure, the corresponding
alarm signal, nALARM0 or nALARM1, is latched LOW. A HIGH-
to-LOW transition on input signal nALARM_RST causes the
alarm outputs to be reset HIGH, and the primary clock input is
selected as the reference clock. Otherwise, an internal pull-up
holds nALARM_RST HIGH, and the IDCS flags remain un-
changed. If n_ALARM_RST is asserted when both of the alarm
flag outputs are LOW, CLK0 is selected as the reference input.
The device’s internal PLL is able to maintain phase/frequency
alignment, and lock with the input as long as the input used as
the reference clock does not fail.
MANUAL CLOCK SWITCHING
When input signal nMAN/A is driven LOW, the primary clock, as
selected by REF_SEL, is always used as the reference, even
when a clock failure is detected at the reference. In order switch
between CLK0 and CLK1 as the primary clock, the level on
REF_SEL must be driven to the appropriate level.When the level
on REF_SEL is changed, the selection of the new primary clock
will take place, and CLK_IND will be updated to indicate which
clock is now supplying reference. This process serves as a
manual safety mechanism to protect the stability of the PLL when
a failure occurs on the reference.
DYNAMIC CLOCK SWITCHING
When input signal nMAN/A is not driven LOW, an internal pull-
up pulls it HIGH so that Intelligent Dynamic Clock Switching
(IDCS) is enabled. If IDCS is enabled, once a failure occurs on
the primary clock, the ICS879893BI device will automatically de-
select the primary clock as the reference and multiplex in the
secondary clock, but only if it is valid and has no failures. When
a successful switch from primary to secondary has been ac-
complished, CLK_IND will be updated to indicate the new refer-
ence. This process serves as an automatic safety mechanism
to protect the stability of the PLL when a failure occurs on the
reference.
OUTPUT TRANSITIONING
After a successful manual or IDCS initiated clock switch, the
ICS879893BI’s internal PLL will begin slewing to phase/frequency
alignment, and will eventually achieve lock with the new input
with minimal phase disturbance at the outputs.
MASTER RESET OPERATION
When input signal nOE/MR is driven HIGH, the output clocks,
QA0:QA5, are tri-stated and the ICS879893BI’s internal divid-
ers are reset. Otherwise, nOE/MR is pulled LOW and the output
clocks and internal dividers are enabled.
RECOMMENDED POWERUP SEQUENCE
1. Hold nOE/MR HIGH, drive nMAN/A LOW, and drive
REF_SEL to the desired value during power up in order to reset
internal dividers, tristate the outputs, select manual switching
mode, and select the primary input clock.
2. Once powered up, assuming a stable clock free of failures is
present at the primary input, the PLL will begin phase/frequency
slewing as it attempts to achieve lock with the input reference
clock.
3. Transition nALARM_RST HIGH-to-LOW to reset nALARM0
and nALARM1 alarm flag outputs.
4. (Optional) Drive nMAN/A HIGH to enable IDCS mode.
ALTERNATE POWERUP SEQUENCE
If both input clocks are valid before power up, the part may be
powered up in ICDS mode.
1. Hold nOE/MR HIGH and drive REF_SEL to the desired value
during power up in order to reset internal dividers, tristate the
outputs, and select the primary input clock. Leave nMAN/A float-
ing, and an internal pull-up at that input will enable IDCS mode.
2. Once powered up, the PLL will begin phase/frequency slewing
as it attempts to achieve lock with the input reference clock.
3. Transition nALARM_RST HIGH-to-LOW to reset nALARM0
and nALARM1 alarm flag outputs.
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