- 您现在的位置：买卖IC网 > PDF目录67111 > ICS9112F-17-T-LF (INTEGRATED DEVICE TECHNOLOGY INC) PLL BASED CLOCK DRIVER, 9 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16 PDF资料下载
参数资料
| 型号： | ICS9112F-17-T-LF |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟及定时 |
| 英文描述： | PLL BASED CLOCK DRIVER, 9 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16 |
| 封装： | 0.150 INCH, SSOP-16 |
| 文件页数： | 4/9页 |
| 文件大小： | 222K |
| 代理商： | ICS9112F-17-T-LF |
4
ICS9112-17
Preliminary Product Preview
Electrical Characteristics - OUT PUT
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-10%; CL = 20 - 30 pF (unless otherwise stated)
PARAMETER
SYM BOL
CONDITIONS
MIN
TYP
M AX
UNITS
Output Impedance
RDSP
VO = VDD*(0.5)
10
24
Output Impedance
RDSN
VO = VDD*(0.5)
10
24
Output High Voltage
VOH
IOH = 8 mA
2.4
2.9
5.0
V
Output Low Voltage
VOL
IOL = 8 mA
0.25
0.4
V
Rise Time
1
Tr
VOL = 0.8 V, VOH = 2.0 V
1.2
2.0
ns
Fall Time
1
Tf
VOH = 2.0 V, VOL = 0.8 V
1.2
2.0
ns
Duty Cycle
1
Dt
VT = 1.4V;Cl=30pF
40
50
60
%
Duty Cycle
1
Dt
VT = Vdd/2; Fout<66.6MHz
45
50
55
%
Tcyc-cyc
at 66M Hz ; loaded Outputs
250
ps
Tcyc-cyc
>66M Hz ; loaded Outputs
200
ps
Absolute Jitter
1
Tjabs
10000 cycles; Cl=30pF
-100
70
100
ps
Jitter; 1-Sigma
1
Tj1s
10000 cycles; Cl=30pF
14
30
ps
Skew
1
Tsk
VT = 1.4 V (Window) Output to Output
250
ps
Delay Input-Output
1
DR1
VT = 14 V
0
700
ps
Cycle to Cycle jitter
1
Electrical Characteristics - OUTPUT
TA = 0 - 70C; VDD = VDDL = 5.0 V +/-10%; CL = 20 - 30 pF (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS
Output Impedance
RDSP
VO = VDD*(0.5)
10
24
Output Impedance
RDSN
VO = VDD*(0.5)
10
24
Output High Voltage
VOH
IOH = 8 mA
2.4
2.9
5.0
V
Output Low Voltage
VOL
IOL = 8 mA
0.25
0.4
V
Rise Time
1
Tr
VOL = 0.8 V, VOH = 2.0 V
0.8
1.5
ns
Fall Time
1
Tf
VOH = 2.0 V, VOL = 0.8 V
1.0
1.5
ns
Duty Cycle
1
Dt
VT = 1.4V;Cl=30pF
40
50
60
%
Tcyc-cyc
at 66MHz , Loaded Outputs
250
ps
Tcyc-cyc
>66MHz , Loaded Outputs
200
ps
Absolute Jitter
1
Tjabs
10000 cycles; Cl=30pF
-100
60
100
ps
Jitter; 1-Sigma
1
Tj1s
10000 cycles; Cl=30pF
14
30
ps
Skew
1
Tsk
VT = 1.4 V (Window) Output to Output
250
ps
Delay Input-Output
1
DR1
VT = 14 V
0
700
ps
1 Guaranteed by design, not 100% tested in production.
Cycle to Cycle jitter
1
相关PDF资料 |
PDF描述 |
|---|---|
| ICS9112F-17 | 91 SERIES, PLL BASED CLOCK DRIVER, 9 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16 |
| ICS9112M-06 | 91 SERIES, PLL BASED CLOCK DRIVER, 5 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8 |
| ICS9112YM-28-T | LOW SKEW CLOCK DRIVER, 5 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8 |
| ICS9120M-45LF | 50 MHz, OTHER CLOCK GENERATOR, PDSO8 |
| ICS9120M-45 | 50 MHz, OTHER CLOCK GENERATOR, PDSO8 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ICS9112M-06 | 制造商:Integrated Device Technology Inc 功能描述: |
| ICS9112M-07 | 制造商:ICS 制造商全称:ICS 功能描述:Low Skew Output Buffer |
| ICS9112M-22 | 功能描述:IC CLK BUFFER DVR 133MHZ 8-SOIC RoHS:否 类别:集成电路 (IC) >> 时钟/计时 - 时钟缓冲器，驱动器 系列:- 标准包装:74 系列:- 类型:扇出缓冲器（分配） 电路数:1 比率 - 输入:输出:1:10 差分 - 输入:输出:是/是 输入:HCSL, LVCMOS, LVDS, LVPECL, LVTTL 输出:HCSL，LVDS 频率 - 最大:400MHz 电源电压:3 V ~ 3.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:32-VFQFN 裸露焊盘 供应商设备封装:32-QFN（5x5） 包装:管件 |
| ICS9112M-31 | 制造商:ICS 制造商全称:ICS 功能描述:Frequency Generator for Fibre Channel Systems |
| ICS9112M-32 | 制造商:ICS 制造商全称:ICS 功能描述:Frequency Generator for Fibre Channel Systems |
发布紧急采购，3分钟左右您将得到回复。