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参数资料
| 型号： | ICS9112F-17-T |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟及定时 |
| 英文描述： | PLL BASED CLOCK DRIVER, 9 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16 |
| 封装： | 0.150 INCH, SSOP-16 |
| 文件页数： | 1/9页 |
| 文件大小： | 222K |
| 代理商： | ICS9112F-17-T |
Integrated
Circuit
Systems, Inc.
General Description
Features
ICS9112-17
Block Diagram
Low Skew Output Buffer
9112A-17 Rev D 9/17/99
Pin Configuration
16 pin SSOP
Zero input - output delay
Frequency range 25 - 133 MHz (3.3V)
High loop filter bandwidth ideal for Spread Spectrum
applications.
Less than 200 ps cycle to cycle Jitter
Skew controlled outputs
Skew less than 250 ps between outputs
Available in 16 pin, 150 mil SSOP package
The ICS9112-17 is a high performance, low skew, low jitter
zero delay buffer. It uses a phase lock loop (PLL) technology
to align, in both phase and frequency, the REF input with the
CLKOUT signal.
It is designed to distribute high speed
clocks in PC systems operating at speeds from 25 to
133 MHz.
ICS9112-17 is a zero delay buffer that provides
synchronization between the input and output. The
synchronization is established via CLKOUT feed back to the
input of the PLL. Since the skew between the input and
output is less than +/- 350 pS, the part acts as a zero delay
buffer.
The ICS9112-17 has two banks of four outputs controlled by
two address lines. Depending on the selected address line,
bank B or both banks can be put in a tri-state mode. In this
mode, the PLL is still running and only the output buffers are
put in a high impedance mode. The test mode shuts off the
PLL and connects the input directly to the output buffers (see
table below for functionality).
The ICS9112-17 comes in a sixteen pin 150 mil SOIC or 16
pin SSOP package. In the absence of REF input, will be in the
power down mode. In this mode, the PLL is turned off and the
output buffers are pulled low. Power down mode provides
the lowest power consumption for a standby condition.
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Functionality
Preliminary Product Preview
PRODUCT PREVIEW documents contain information on new
products in the sampling or preproduction phase of development.
Characteristic data and other specifications are subject to change
without notice.
相关PDF资料 |
PDF描述 |
|---|---|
| ICS9112F-17-T-LF | PLL BASED CLOCK DRIVER, 9 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16 |
| ICS9112F-17 | 91 SERIES, PLL BASED CLOCK DRIVER, 9 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16 |
| ICS9112M-06 | 91 SERIES, PLL BASED CLOCK DRIVER, 5 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8 |
| ICS9112YM-28-T | LOW SKEW CLOCK DRIVER, 5 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8 |
| ICS9120M-45LF | 50 MHz, OTHER CLOCK GENERATOR, PDSO8 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ICS9112M-06 | 制造商:Integrated Device Technology Inc 功能描述: |
| ICS9112M-07 | 制造商:ICS 制造商全称:ICS 功能描述:Low Skew Output Buffer |
| ICS9112M-22 | 功能描述:IC CLK BUFFER DVR 133MHZ 8-SOIC RoHS:否 类别:集成电路 (IC) >> 时钟/计时 - 时钟缓冲器，驱动器 系列:- 标准包装:74 系列:- 类型:扇出缓冲器（分配） 电路数:1 比率 - 输入:输出:1:10 差分 - 输入:输出:是/是 输入:HCSL, LVCMOS, LVDS, LVPECL, LVTTL 输出:HCSL，LVDS 频率 - 最大:400MHz 电源电压:3 V ~ 3.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:32-VFQFN 裸露焊盘 供应商设备封装:32-QFN（5x5） 包装:管件 |
| ICS9112M-31 | 制造商:ICS 制造商全称:ICS 功能描述:Frequency Generator for Fibre Channel Systems |
| ICS9112M-32 | 制造商:ICS 制造商全称:ICS 功能描述:Frequency Generator for Fibre Channel Systems |
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