参数资料
型号: ICS9112YG-27LF-T
厂商: INTEGRATED DEVICE TECHNOLOGY INC
元件分类: 时钟及定时
英文描述: LOW SKEW CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8
封装: 0.173 INCH, MO-153, LEAD FREE, TSSOP-8
文件页数: 1/8页
文件大小: 105K
代理商: ICS9112YG-27LF-T
Integrated
Circuit
Systems, Inc.
General Description
Features
ICS9112-27
0055G—04/26/05
Block Diagram
Low Skew PCI / PCI-X Buffer
Pin Configuration
Frequency range 0 - 140 MHz (3.3V)
Less than 200 ps Jitter between outputs
Skew controlled outputs < 100 ps
Distribute one clock input to one bank of four
outputs
3.3V ±10% operation
Available in 8 pin TSSOP, and SOIC packages.
The ICS9112-27 is a high performance, low skew, low jitter
PCI / PCI-X clock driver. It is designed to distribute high
speed signals in PCI / PCI-X applications operating at
speeds from 0 to 140 MHz.
The ICS9112-27 is characterized for operation from -40°C
to 85°C for automotive and industrial applications.
8 pin TSSOP & SOIC
CLK_IN
OE
CLK0
GND
CLK3
CLK2
VDD
CLK1
ICS9112-27
1
2
3
4
8
7
6
5
CLK_IN
CLK0
CLK1
CLK2
CLK3
LOGIC
CONTROL
OE
Pin Descriptions
S
T
U
P
N
IS
T
U
P
T
U
O
N
I
_
K
L
CE
O)
0
:
3
(
K
L
C
00
e
t
a
t
s
i
r
T
01
0
10
e
t
a
t
s
i
r
T
11
1
Functionality Table
R
E
B
M
U
N
I
PE
M
A
N
I
PE
P
Y
TN
O
I
T
P
I
R
C
S
E
D
1N
I
_
K
L
CN
I.
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c
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u
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r
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r
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p
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I
2E
ON
I
s
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u
p
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c
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w
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s
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O
n
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h
W
.
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l
b
a
n
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t
u
p
t
u
O
30
K
L
CT
U
Ot
u
p
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u
o
k
c
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c
d
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f
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4D
N
GR
W
Pd
n
u
o
r
G
51
K
L
CT
U
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6D
D
VR
W
PV
3
.
3
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w
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P
72
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