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参数资料
| 型号： | ICS91305LYG-T |
| 元件分类： | 时钟及定时 |
| 英文描述： | PLL BASED CLOCK DRIVER, 5 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8 |
| 封装： | 0.173 INCH, MO-153, TSSOP-8 |
| 文件页数： | 4/7页 |
| 文件大小： | 66K |
| 代理商： | ICS91305LYG-T |
4
ICS91305I
0691C—07/28/03
Switching Characteristics
Notes:
1.
Guaranteed by design and characterization. Not subject to 100% test.
2.
REF input has a threshold voltage of 1.4V
3.
All parameters expected with loaded outputs
PARAMETER
SYMBOL
CONDITION
MIN
TYP
MAX
UNITS
Output period
t1
With CL=30pF
100.00
(10)
7.5
(133)
ns
(MHz)
Input period
t1
With CL=30pF
100.00
(10)
7.5
(133)
ns
(MHz)
Duty Cycle1
Dt1
Measured at 1.4V; CL=30pF
40.0
50
60
%
Duty Cycle1
Dt2
Measured at VDD/2 Fout
<66.6MHz
45
50
55
%
Rise Time1
tr1
Measured between 0.8V and 2.0V:
CL=30pF
1.2
1.5
ns
Fall Time1
tf1
Measured between 2.0V and 0.8V;
CL=30pF
1.2
1.5
ns
Delay, REF Rising
Edge to CLKOUT
Rising Edge1, 2
Dr1
Measured at 1.4V
0
±350
ps
Output to Output
Skew1
Tskew
All outputs equally loaded,
CL=20pF
250
ps
Device to Device
Skew1
Tdsk-Tdsk
Measured at VDD/2 on the
CLKOUT pins of devices
0
700
ps
Cycle to Cycle
Jitter1
Tcyc-Tcyc
Measured at 66.66 MHz, loaded
outputs
200
ps
PLL Lock Time1
t
LOCK
Stable power supply, valid clock
presented on REF pin
1.0
ms
Jitter; Absolute
Jitter1
Tjabs
@ 10,000 cycles
C
L = 30pF
-200
70
200
ps
Jitter; 1 - Sigma1
Tj1s
@ 10,000 cycles
C
L = 30pF
14
60
ps
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| ICS91305YGLF-T | 91305 SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8 |
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相关代理商/技术参数 |
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| ICS91305YGILF-T | 制造商:ICSI 制造商全称:Integrated Circuit Solution Inc 功能描述:High Performance Communication Buffer |
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| ICS91305YMILF-T | 制造商:ICSI 制造商全称:Integrated Circuit Solution Inc 功能描述:High Performance Communication Buffer |
| ICS91305YMLFT | 制造商:ICS 制造商全称:ICS 功能描述:High Performance Communication Buffer |
| ICS91309 | 制造商:ICS 制造商全称:ICS 功能描述:High performance Communication Buffer |
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