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参数资料
| 型号： | ICS91305YG-T |
| 元件分类： | 时钟及定时 |
| 英文描述： | 91305 SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8 |
| 封装： | 4.40 MM, 0.65 MM PITCH, MO-153, TSSOP-8 |
| 文件页数： | 1/7页 |
| 文件大小： | 70K |
| 代理商： | ICS91305YG-T |
Integrated
Circuit
Systems, Inc.
General Description
Features
ICS91305
0092F—08/20/04
Block Diagram
High Performance Communication Buffer
Pin Configuration
Zero input - output delay
Frequency range 10 - 133 MHz (3.3V)
5V tolerant input REF
High loop filter bandwidth ideal for Spread
Spectrum applications.
Less than 200 ps Jitter between outputs
Skew controlled outputs
Skew less than 250 ps between outputs
Available in 8 pin 150 mil SOIC & 173 mil
TSSOP packages
3.3V ±10% operation
The ICS91305 is a high performance, low skew, low jitter
clock driver. It uses a phase lock loop (PLL) technology
to align, in both phase and frequency, the REF input with
the CLKOUT signal. It is designed to distribute high speed
clocks in communication systems operating at speeds
from 10 to 133 MHz.
ICS91305 is a zero delay buffer that provides
synchronization between the input and output. The
synchronization is established via CLKOUT feed back to
the input of the PLL. Since the skew between the input and
output is less than +/- 350 pS, the part acts as a zero delay
buffer.
The ICS91305 comes in an eight pin 150 mil SOIC
package. It has five output clocks. In the absence of REF
input, will be in the power down mode. In this mode, the
PLL is turned off and the output buffers are pulled low.
Power down mode provides the lowest power consumption
for a standby condition.
8 pin SOIC & TSSOP
REF
CLK2
CLK1
GND
CLKOUT
CLK4
VDD
CLK3
ICS91305
1
2
3
4
8
7
6
5
相关PDF资料 |
PDF描述 |
|---|---|
| ICS91305YGLF-T | 91305 SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8 |
| ICS91305YM-T | 91305 SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8 |
| ICS91305YMILF-T | 91305 SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8 |
| ICS91309YFILF-T | PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16 |
| ICS91309YFLF-T | PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ICS91305YMILF-T | 制造商:ICSI 制造商全称:Integrated Circuit Solution Inc 功能描述:High Performance Communication Buffer |
| ICS91305YMLFT | 制造商:ICS 制造商全称:ICS 功能描述:High Performance Communication Buffer |
| ICS91309 | 制造商:ICS 制造商全称:ICS 功能描述:High performance Communication Buffer |
| ICS91309AGILF | 功能描述:IC CLK BUFFER ZD PLL 16TSSOP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:- 标准包装:2,000 系列:- 类型:PLL 时钟发生器 PLL:带旁路 输入:LVCMOS，LVPECL 输出:LVCMOS 电路数:1 比率 - 输入:输出:2:11 差分 - 输入:输出:是/无 频率 - 最大:240MHz 除法器/乘法器:是/无 电源电压:3.135 V ~ 3.465 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:32-LQFP 供应商设备封装:32-TQFP（7x7） 包装:带卷 (TR) |
| ICS91309AGILFT | 功能描述:IC CLK BUFFER ZD PLL 16TSSOP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:- 标准包装:2,000 系列:- 类型:PLL 时钟发生器 PLL:带旁路 输入:LVCMOS，LVPECL 输出:LVCMOS 电路数:1 比率 - 输入:输出:2:11 差分 - 输入:输出:是/无 频率 - 最大:240MHz 除法器/乘法器:是/无 电源电压:3.135 V ~ 3.465 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:32-LQFP 供应商设备封装:32-TQFP（7x7） 包装:带卷 (TR) |
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