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参数资料
| 型号： | ICS91305YG-T |
| 元件分类： | 时钟及定时 |
| 英文描述： | 91305 SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8 |
| 封装： | 4.40 MM, 0.65 MM PITCH, MO-153, TSSOP-8 |
| 文件页数： | 5/7页 |
| 文件大小： | 70K |
| 代理商： | ICS91305YG-T |
5
ICS91305
0092F—08/20/04
Output to Output Skew
The skew between CLKOUT and the CLK(1-4) outputs is not dynamically adjusted by the PLL. Since CLKOUT is one
of the inputs to the PLL, zero phase difference is maintained from REF to CLKOUT. If all outputs are equally loaded,
zero phase difference will maintained from REF to all outputs.
If applications requiring zero output-output skew, all the outputs must equally loaded.
If the CLK(1-4) outputs are less loaded than CLKOUT, CLK(1-4) outputs will lead it; and if the CLK(1-4) is more loaded
than CLKOUT, CLK(1-4) will lag the CLKOUT.
Since the CLKOUT and the CLK(1-4) outputs are identical, they all start at the same time, but different loads cause
them to have different rise times and different times crossing the measurement thresholds.
REF input and
all outputs
loaded Equally
REF input and CLK(1-4)
outputs loaded equally, with
CLKOUT loaded More.
REF input and CLK(1_4)
outputs loaded equally, with
CLKOUT loaded Less.
Timing diagrams with different loading configurations
相关PDF资料 |
PDF描述 |
|---|---|
| ICS91305YGLF-T | 91305 SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8 |
| ICS91305YM-T | 91305 SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8 |
| ICS91305YMILF-T | 91305 SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8 |
| ICS91309YFILF-T | PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16 |
| ICS91309YFLF-T | PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ICS91305YMILF-T | 制造商:ICSI 制造商全称:Integrated Circuit Solution Inc 功能描述:High Performance Communication Buffer |
| ICS91305YMLFT | 制造商:ICS 制造商全称:ICS 功能描述:High Performance Communication Buffer |
| ICS91309 | 制造商:ICS 制造商全称:ICS 功能描述:High performance Communication Buffer |
| ICS91309AGILF | 功能描述:IC CLK BUFFER ZD PLL 16TSSOP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:- 标准包装:2,000 系列:- 类型:PLL 时钟发生器 PLL:带旁路 输入:LVCMOS，LVPECL 输出:LVCMOS 电路数:1 比率 - 输入:输出:2:11 差分 - 输入:输出:是/无 频率 - 最大:240MHz 除法器/乘法器:是/无 电源电压:3.135 V ~ 3.465 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:32-LQFP 供应商设备封装:32-TQFP（7x7） 包装:带卷 (TR) |
| ICS91309AGILFT | 功能描述:IC CLK BUFFER ZD PLL 16TSSOP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:- 标准包装:2,000 系列:- 类型:PLL 时钟发生器 PLL:带旁路 输入:LVCMOS，LVPECL 输出:LVCMOS 电路数:1 比率 - 输入:输出:2:11 差分 - 输入:输出:是/无 频率 - 最大:240MHz 除法器/乘法器:是/无 电源电压:3.135 V ~ 3.465 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:32-LQFP 供应商设备封装:32-TQFP（7x7） 包装:带卷 (TR) |
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