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参数资料
| 型号： | ICS9148F-25 |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 83.3 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封装： | 0.300 INCH, SSOP-48 |
| 文件页数： | 9/13页 |
| 文件大小： | 537K |
| 代理商： | ICS9148F-25 |
5
ICS9148-25
CPU3.3_2.5#
This Input pin controls the CPU and IOAPIC output buffer
strength for skew matching CPU and SDRAM outputs to
compensate for the external VDDL supply condition. It is
important to use this function when selecting power supply
requirements for VDDL1,2. Alogic “0” (ground) will indicate
2.5V operation and a logic “1” will indicate 3.3V operation.
This pin has an internal pull-up to VDD. This pin is a latched
input.
PD#
This is an asynchronous active Low Input pin used to Power
Down the device into a Low Power state by not removing the
power supply. The internal Clocks are disabled and the VCO
and Crystal are stopped. Powered Down will also place all the
Outputs in a low state at the end of their current cycle. The
latency of Power Down will not be greater than 3ms. This pin
is a Full-time input with a pull-up to VDD.
CPU_STOP#
This is a active Low Input pin used to stop the CPUCLK
clocks in an active low state. All other clocks will continue to
run while this function is enabled. The CPUCLK’s will have a
turn OFF latency and a turn ON latency of 2 or 3 CPU clocks.
This pin is a Full-time input with a pull-up to VDD.
PCI_STOP#
This is a synchronous active Low Input pin used to stop the
PCICLK (0:5) clocks in a low state. It will not effect PCICLK_F
or any other outputs. There is only one full PCI clock output
for Turn OFF or Turn ON latency. This pin is a Full-time input
with a pull-up to VDD.
Technical Pin Function Descriptions
SSM (0:1)
These pins define the input condition for the Spread Spectrum
amount of modulation. See Spread Spectrum functionality
table. Note that spreading is only done on the CPU/SDRAM/
PCI clocks no modulation is done on the REF, IOAPIC or
PLL2 (24, 48MHz) outputs.
These latched input pins are defined at power-on for logic Hi
or logic Low condition by external pull-up or pull-down
resistors, or the internal pull-up resistor to VDD. See shared
pin operation of Input/output pins on next page.
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| ICS9148F-32 | 100 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| ICS9148F-58LF | 133.3 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| ICS9148F-58LF | 133.3 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| ICS9148F-58 | 133.3 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| ICS9148F-93LF | 100 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ICS9148F-25T | 功能描述:IC CLK SYNTHESIZER CHIP 48-SSOP RoHS:否 类别:集成电路 (IC) >> 时钟/计时 - 专用 系列:- 标准包装:28 系列:- 类型:时钟/频率发生器 PLL:是 主要目的:Intel CPU 服务器 输入:时钟 输出:LVCMOS 电路数:1 比率 - 输入:输出:3:22 差分 - 输入:输出:无/是 频率 - 最大:400MHz 电源电压:3.135 V ~ 3.465 V 工作温度:0°C ~ 85°C 安装类型:表面贴装 封装/外壳:64-TFSOP （0.240"，6.10mm 宽） 供应商设备封装:64-TSSOP 包装:管件 |
| ICS9148F-26 | 制造商:ICS 制造商全称:ICS 功能描述:Frequency Generator & Integrated Buffers for PENTIUM/ProTM |
| ICS9148F-32 | 制造商:ICS 制造商全称:ICS 功能描述:Pentium/ProTM System Clock Chip |
| ICS9148F-37 | 制造商:ICS 制造商全称:ICS 功能描述:Frequency Generator & Integrated Buffers for PENTIUM/ProTM |
| ICS9148F-46 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:CPU System Clock Generator |
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