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参数资料
| 型号： | ICS9148YF-12LF |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 66.6 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封装： | 0.300 INCH, SSOP-48 |
| 文件页数： | 1/18页 |
| 文件大小： | 476K |
| 代理商： | ICS9148YF-12LF |
Integrated
Circuit
Systems, Inc.
General Description
Features
ICS9148-12
Block Diagram
Pentium/ProTM System Clock Chip
0123G—03/20/02
Pentium is a trademark on Intel Corporation.
CPU outputs are stronger drive for multiple loads
per pin (ie CPU and NB on one pin)
Generates system clocks for CPU, IOAPIC,
SDRAM, PCI, plus 14.314 MHz REF(0:1), USB,
Plus Super I/O
Supports single or dual processor systems
I
2C serial configuration interface provides output
clock disabling and other functions
MODE input pin selects optional power
management input control pins
Two fixed outputs separately selectable as 24 or
48MHz
Separate 2.5V and 3.3V supply pins
2.5V or 3.3V outputs: CPU, IOAPIC
3.3V outputs: SDRAM, PCI, REF, 48/24 MHz
CPU 3.3_2.5# logic pin to adjust output strength
No power supply sequence requirements
Uses external 14.318MHz crystal
48 pin 300 mil SSOP and 240 mil TSSOP
Output enable register
for serial port control:
1 = enable
0 = disable
The ICS9148-12 is a Clock Synthesizer chip for Pentium
and PentiumPro CPU based Desktop/Notebook systems
that will provide all necessary clock timing.
Features include four strong CPU, seven PCI and eight
SDRAM clocks. Two reference outputs are available
equal to the crystal frequency. Stronger drive CPUCLK
outputs typically provide greater than 1 V/ns slew rate
into 20pF loads. This device meets rise and fall
requirements with 2 loads per CPU output (ie, one clock
to CPU and NB chipset, one clock to two L2 cache
inputs).
PWR_DWN# pin allows low power mode by stopping
crystal OSC and PLL stages. For optional power
management, CPU_STOP# can stop CPU (0:3) clocks
and PCI_STOP# will stop PCICLK (0:5) clocks. CPU
and IOAPIC output buffer strength controlled by CPU
3.3_2.5# pin to match VDDL voltage.
PCICLK outputs typically provide better than 1V/ns
slew rate into 30pF loads while maintaining 50±5% duty
cycle. The REF clock outputs typically provide better
than 0.5V/ns slew rates.
The ICS9148-12 accepts a 14.318MHz reference crystal
or clock as its input and runs on a 3.3V core supply.
Functionality
VDD (1:4) 3.3V±10%, VDDL1, 2 2.5±5% or 3.3±10% 0-70
°C
Crystal (X1, X2) = 14.31818 MHz
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Pin Configuration
48-Pin SSOP & TSSOP
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ICS9148YF-17-T | 制造商:ICS 制造商全称:ICS 功能描述:Frequency Generator & Integrated Buffers for PENTIUM/ProTM |
| ICS9148YF-36 | 制造商:ICS 制造商全称:ICS 功能描述:Frequency Generator & Integrated Buffers for PENTIUM/ProTM |
| ICS9148YF-46 | 制造商:ICS 制造商全称:ICS 功能描述:Pentium/ProTM System Clock Chip |
| ICS9148YF-60 | 制造商:ICS 制造商全称:ICS 功能描述:Pentium/ProTM System Clock Chip |
| ICS9148YF-82 | 制造商:ICS 制造商全称:ICS 功能描述:Frequency Generator & Integrated Buffers for PENTIUM/ProTM |
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