
2
ICS9158-05
Advanced Information
Pin Configuration
Pin Descriptions for ICS9158-05
24-Pin SOIC
* Input pin has internal pull-up to VDD.
Functionality
VDD = +5V±10%, TA=0°C to 70°C unless otherwise stated
PD# forces all outputs low and powers-down the oscillator and PLL
circuitry, minimizing power consumption. In order to ensure glitch-free start
and stop of the CPU and BUS clocks, PD# should be asserted after the
CPU and BUS clocks have stopped, and be deasserted 10ms (maximum
PLL lock time) prior to starting the clocks.
OE
PD#
FLOPPY (MHz)
KEYBD (MHz)
1
24
12
1
0
Low
0
X
Tristate
PIN NUMBER
PIN NAME
TYPE
DESCRIPTION
1
REFCLK
OUT
14.318 clock output.
2
X2
OUT
Crystal connection, which includes output crystal load capacitance.
3X1
IN
Crystal connection, which includes crystal load capacitance and feedback bias
for a nominal 14.31818 MHz parallel-resonance 12pF crystal.
4
VDD
PWR
Digital POWER SUPPLY.
5
GND
PWR
Digital GROUND.
6
KEYBD
OUT
12 MHz keyboard clock output.
7
FLOPPY
OUT
24 MHz floppy disk clock output.
8
BUS0
OUT
BUS clock output.
9
AGND
PWR
ANALOG GROUND.
10
OE
IN
OUTPUT ENABLE. Tristates all outputs when low.*
11
BUS1
OUT
BUS clock output.
12
GND
PWR
Digital GROUND.
13
CPU0
OUT
CPU clock output.
14
CPU1
OUT
CPU clock output.
15
PD#
IN
Power-down input shuts off both PLL stages when low.*
16
AVDD
PWR
ANALOG power supply.
17
BUS2
OUT
CPU clock output.
18
BUS3
OUT
BUS clock output.
19
GND
PWR
Digital GROUND.
20
VDD
PWR
Digital POWER SUPPLY.
21
CPU2
OUT
CPU clock output.
22
BUS4
OUT
BUS clock output.
23
FS1
IN
Clock frequency select #1.*
24
FS0
IN
Clock frequency select #0.*
OE
PD#
FS1
FS0
CPU
Ratio
X1,X2,
REF
(MHz)
CPU
(0:2)
(MHz)
BUS
(0:4)
(MHz)
1
0
14/4xX1
14.318
50
25
1
0
1
14/3xX1
14.318
66.7
33.3
1
0
42/10xX1
14.318
60
30
1
(STOP)
14.318
Low
10
X
(PWR
DOWN)
Low
*Low
0
X
-
Tristate