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参数资料
| 型号： | ICS9158-05M |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 66.7 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO24 |
| 封装： | SOIC-24 |
| 文件页数： | 6/7页 |
| 文件大小： | 174K |
| 代理商： | ICS9158-05M |
6
ICS9158-05
Advanced Information
Frequency Transitions
A key feature of the ICS9158-05 is its ability to provide
smooth, glitch-free frequency transitions on the CPU and
BUS clocks when the frequency select pins are changed. The
frequency transition rate does not violate the Intel 486 or
Pentium specification of less than 0.1% frequency change
per clock period.
ICS9158-05 CPU Clock DecodingTable
(using 14.318 MHz input. All frequencies in MHz)
VDD=5V±10% or 3.3V±10%, TEMP=0-70°C
PD# forces all outputs low and powers-down the oscillator
and PLL circuitry, minimizing power consumption. In order
to ensure glitch-free start and stop of the CPU and BUS
clocks, PD# should be asserted after the CPU and BUS clocks
have stopped, and be deasserted 10ms (maximum PLL lock
time) prior to starting the clocks.
Using an Input Clock as a Reference
The ICS9158-05 is designed to accept a 14.318 MHz crystal
as the input reference. With some external changes, it is
possi-ble to use a crystal oscillator or other clock sources.
Please see application note AAN04 for details on driving the
ICS9158-05 with a clock.
OE
PD#
FS1
FS0
CPU
Ratio
X1,X2,
REF
(MHz)
CPU
(0:2)
(MHz)
BUS
(0:4)
(MHz)
1100
14/4xX1
14.318
50
25
1101
14/3xX1
14.318
66.7
33.3
1110
42/10xX1
14.318
60
30
1111
(STOP)
14.318
Low
10
X
(PWR
DOWN)
Low
*Low
0
X
-
Tristate
OE
PD#
FLOPPY (MHz)
KEYBD (MHz)
1
24
12
1
0
Low
0
X
Tristate
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| ICS9159F-12LF | 66.47 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO28 |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ICS9158-06M | 制造商:未知厂家 制造商全称:未知厂家 功能描述:CPU System Clock Generator |
| ICS9158-07 | 制造商:ICS 制造商全称:ICS 功能描述:Frequency Generator and Integrated Buffer |
| ICS9158-07M | 制造商:ICS 制造商全称:ICS 功能描述:Frequency Generator and Integrated Buffer |
| ICS9158-07N | 制造商:未知厂家 制造商全称:未知厂家 功能描述:CPU System Clock Generator |
| ICS9158M01 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Peripheral IC |
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