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参数资料
| 型号： | ICS9169CM-27 |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 83.3 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO32 |
| 封装： | SOIC-32 |
| 文件页数： | 5/10页 |
| 文件大小： | 293K |
| 代理商： | ICS9169CM-27 |
4
ICS9169C-27
0218D—10/06/05
Shared Pin Operation - Input/Output Pins 5, 12, 13 and
32 on the ICS9169C-27 serve as dual signal functions to
the device. During initial power-up, they act as input pins.
The logic level (voltage) that is present on these pins at
this time is read and stored into a 4-bit internal data latch.
At the end of Power-On reset, (see AC characteristics for
timing values), the device changes the mode of operation
for these pins to an output function. In this mode the pins
produce the specified buffered clocks to external loads.
To program (load) the internal configuration register for
these pins, a resistor is connected to either the VDD
(logic 1) power supply or the GND (logic 0) voltage
potential. A 10 Kilohm(10K) resistor is used to provide
both the solid CMOS programming voltage needed during
the power-up programming period and to provide an
insignificant load on the output clock during the
subsequent operating period.
Figs. 1 and 2 show the recommended means of
implementing this function. In Fig. 1 either one of the
resistors is loaded onto the board (selective stuffing) to
configure the device.s internal logic. Figs. 2a and b
provide a single resistor loading option where either solder
spot tabs or a physical jumper header may be used.
These figures illustrate the optimal PCB physical layout
options. These configuration resistors are of such a large
ohmic value that they do not effect the low impedance
clock signals. The layouts have been optimized to provide
as little impedance transition to the clock signal as
possible, as it passes through the programming resistor
pad(s).
Shared Pin Operation -
Input/Output Pins
The ICS9169C-27 includes a production test
verification mode of operation. This requires that the
FS0 and FS1 pins be programmed to a logic high and
the FS2 pin be programmed to a logic low(see Shared
Pin Operation section). In this mode the device will
output the following frequencies.
Test Mode Operation
Note: REF is the frequency of either the crystal
connected between the devices X1and X2 or, in the
case of a device being driven by an external reference
clock, the frequency of the reference (or test) clock on
the device.s X1 pin.
Frequency
REF
REF/2
REF/4
REF2
BSEL=1
REF/4
BSEL=0
REF/3
CPU (1:2)
BUS (1:6)
Pin
REF
48MHz
24MHz
(Resistors are surface mount devices
shown schematically between 5.m. pads)
*use only one programming resistor
Fig. 1
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ICS9169CM-271 | 制造商:ICS 制造商全称:ICS 功能描述:Frequency Generator for Pentium⑩ Based Systems |
| ICS9169CM-272 | 制造商:ICS 制造商全称:ICS 功能描述:Frequency Generator for Pentium⑩ Based Systems |
| ICS9169CM-273 | 制造商:ICS 制造商全称:ICS 功能描述:Frequency Generator for Pentium⑩ Based Systems |
| ICS9169F-01 | 制造商:ICS 制造商全称:ICS 功能描述:Frequency Generator and Integrated Buffers for Intel Pentium and Pentium ProTM mPs |
| ICS9169F-03 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:CPU System Clock Generator |
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