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参数资料
| 型号： | ICS91730 |
| 英文描述： | Low EMI, Spread Modulating, Clock Generator |
| 中文描述： | 低EMI，扩展调制，时钟发生器 |
| 文件页数： | 4/11页 |
| 文件大小： | 139K |
| 代理商： | ICS91730 |
4
ICS91730
0794D—05/23/05
General I
2
C serial interface information
How to Write:
Controller (host) sends a start bit.
Controller (host) sends the write address D4
(H)
ICS clock will
acknowledge
Controller (host) sends the begining byte location = N
ICS clock will
acknowledge
Controller (host) sends the data byte count = X
ICS clock will
acknowledge
Controller (host) starts sending
Byte N through
Byte N + X -1
(see Note 2)
ICS clock will
acknowledge
each byte
one at a time
Controller (host) sends a Stop bit
How to Read:
Controller (host) will send start bit.
Controller (host) sends the write address D4
(H)
ICS clock will
acknowledge
Controller (host) sends the begining byte
location = N
ICS clock will
acknowledge
Controller (host) will send a separate start bit.
Controller (host) sends the read address D5
(H)
ICS clock will
acknowledge
ICS clock will send the data byte count = X
ICS clock sends
Byte N + X -1
ICS clock sends
Byte 0 through byte X (if X
(H)
was written to byte 8)
.
Controller (host) will need to acknowledge each byte
Controllor (host) will send a not acknowledge bit
Controller (host) will send a stop bit
ICS (Slave/Receiver)
T
Slave Address D4
(H)
WR
ACK
ACK
ACK
ACK
ACK
P
Byte N + X - 1
Data Byte Count = X
Beginning Byte N
stoP bit
X
Index Block Write Operation
Controller (Host)
Beginning Byte = N
WRite
starT bit
T
Slave Address D4
(H)
starT bit
WR
WRite
RT
Slave Address D5
(H)
Repeat starT
RD
ReaD
Beginning Byte N
Byte N + X - 1
N
P
Not acknowledge
stoP bit
ICS (Slave/Receiver)
Controller (Host)
X
ACK
ACK
Data Byte Count = X
ACK
Index Block Read Operation
Beginning Byte = N
ACK
ACK
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