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参数资料
| 型号： | ICS91857AGT |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟及定时 |
| 英文描述： | 91857 SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48 |
| 封装： | 6.10 MM, 0.50 MM PITCH, ROHS COMPLIANT, MO-153, TSSOP-48 |
| 文件页数： | 14/16页 |
| 文件大小： | 164K |
| 代理商： | ICS91857AGT |
7
ICS91857
0494C—08/15/05
Notes:
1.
Refers to transition on noninverting output in PLL bypass mode.
2.
Switching characteristics guaranteed for application frequency range.
3.
Static phase offset shifted by design.
Timing Requirements for DDRI-400
TA = 0 - 70°C; Supply Voltage AVDD, VDD = 2.6V ± 0.1V
PARAMETER
SYMBOL
CONDITIONS
MIN
MAX
UNITS
Max clock frequency
freqop
2.6V ± 0.1V
60
230
MHz
Application Frequency
Range
freqApp
2.6V ± 0.1V
95
220
MHz
Input clock duty cycle
dtin
40
60
%
CLK stabilization
TSTAB
100
s
Switching Characteristics for DDR200/266/333
PARAMETER
SYMBOL
CONDITION
MIN
TYP
MAX
UNITS
Low-to high level
propagation delay time
tPLH
1
CLK_IN to any output
3.5
ns
High-to low level propagation
delay time
tPLL
1
CLK_IN to any output
3.5
ns
Output enable time
tEN
PD# to any output
3
ns
Output disable time
tdis
PD# to any output
3
ns
Period jitter
Tjit (per)
100 - 200 MHz
-75
75
ps
Half-period jitter
t(jit_hper)
100 - 200 MHz
-75
75
Input clock slew rate
t(sir_I)
14
V/ns
Output clock slew rate
t(sl_o)
12
V/ns
Cycle to Cycle Jitter
1
Tcyc-Tcyc
100 - 200 MHz
-75
75
ps
Static Phase Offset
t(spo)
3
-50
0
50
ps
Output to Output Skew
Tskew
100
ps
Pulse skew
Tskewp
100
ps
Timing Requirements for DDR200/266/333
TA = 0 - 70°C; Supply Voltage AVDD, VDD = 2.5V ± 0.2V (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
MAX
UNITS
Max clock frequency
freqop
2.5V ± 0.2V @ 25°C
60
170
MHz
Application Frequency
Range
freqApp
2.5V ± 0.2V @ 25°C
95
170
MHz
Input clock duty cycle
dtin
40
60
%
CLK stabilization
TSTAB
100
s
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