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参数资料
| 型号： | ICS9214DGLF |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟及定时 |
| 英文描述： | 9214 SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO28 |
| 封装： | 0.173 INCH, 0.65 MM PITCH, LEAD FREE, MO-153, TSSOP-28 |
| 文件页数： | 11/18页 |
| 文件大小： | 310K |
| 代理商： | ICS9214DGLF |
2
Integrated
Circuit
Systems, Inc.
ICS9214
0809E—11/17/06
Pin Descriptions
PIN #
PIN NAME
PIN TYPE
DESCRIPTION
1
AVDD2.5
PWR
2.5V Analog Power pin for Core PLL
2
AGND
PWR
Analog Ground pin for Core PLL
3IREFY
IN
This pin establishes the reference current for the differential clock
pairs. This pin requires a fixed precision resistor tied to ground in
order to establish the appropriate current.
4
AGND
PWR
Analog Ground pin for Core PLL
5
CLK_INT
IN
"True" reference clock input.
6
CLK_INC
IN
"Complementary" reference clock input.
7
VDD2.5
PWR
Power supply, nominal 2.5V
8
GND
PWR
Ground pin.
9SMBCLK
IN
Clock pin of SMBUS circuitry, 5V tolerant
10
SMBDAT
I/O
Data pin of SMBUS circuitry, 5V tolerant
11
OE
IN
Active high input for enabling outputs.
0 = tri-state outputs, 1= enable outputs
12
SMB_A0
IN
SMBus address bit 0 (LSB)
13
SMB_A1
IN
SMBus address bit 1
14
BYPASS#/PLL
IN
Input to select Bypass(fan-out) or PLL (ZDB) mode
0 = Bypass mode, 1= PLL mode
15
VDD2.5
PWR
Power supply, nominal 2.5V
16
ODCLK_C3
OUT
"Complementary" side of open drain differential clock output. This
open drain output needs an external resistor network..
17
ODCLK_T3
OUT
"True" side of open drain differential clock output. This open drain
output needs an external resistor network..
18
GND
PWR
Ground pin.
19
ODCLK_C2
OUT
"Complementary" side of open drain differential clock output. This
open drain output needs an external resistor network..
20
ODCLK_T2
OUT
"True" side of open drain differential clock output. This open drain
output needs an external resistor network..
21
GND
PWR
Ground pin.
22
VDD2.5
PWR
Power supply, nominal 2.5V
23
ODCLK_C1
OUT
"Complementary" side of open drain differential clock output. This
open drain output needs an external resistor network..
24
ODCLK_T1
OUT
"True" side of open drain differential clock output. This open drain
output needs an external resistor network..
25
GND
PWR
Ground pin.
26
ODCLK_C0
OUT
"Complementary" side of open drain differential clock output. This
open drain output needs an external resistor network..
27
ODCLK_T0
OUT
"True" side of open drain differential clock output. This open drain
output needs an external resistor network..
28
VDD2.5
PWR
Power supply, nominal 2.5V
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ICS9214DGLFT | 功能描述:IC CLOCK GEN RAMBUS XDR 28-TSSOP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 专用 系列:- 标准包装:28 系列:- 类型:时钟/频率发生器 PLL:是 主要目的:Intel CPU 服务器 输入:时钟 输出:LVCMOS 电路数:1 比率 - 输入:输出:3:22 差分 - 输入:输出:无/是 频率 - 最大:400MHz 电源电压:3.135 V ~ 3.465 V 工作温度:0°C ~ 85°C 安装类型:表面贴装 封装/外壳:64-TFSOP （0.240"，6.10mm 宽） 供应商设备封装:64-TSSOP 包装:管件 |
| ICS9214YGLF-T | 制造商:ICS 制造商全称:ICS 功能描述:Rambus XDR Clock Generator |
| ICS9219 | 制造商:ICS 制造商全称:ICS 功能描述:Direct Rambus Clock Generator Lite |
| ICS9219YGLF-T | 制造商:ICS 制造商全称:ICS 功能描述:Direct Rambus Clock Generator Lite |
| ICS9220 | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:Programmable RambusTM XDRTM Clock Generator |
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