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参数资料
| 型号： | ICS9248YF-135-T |
| 元件分类： | XO, clock |
| 英文描述： | 150 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封装： | 0.300 INCH, SSOP-48 |
| 文件页数： | 15/15页 |
| 文件大小： | 191K |
| 代理商： | ICS9248YF-135-T |
9
ICS9248-135
Third party brands and names are the property of their respective owners.
PCI_STOP# Timing Diagram
PCI_STOP# is an asynchronous input to the ICS9248-135. It is used to turn off the PCICLK clocks for low power operation.
PCI_STOP# is synchronized by the ICS9248-135 internally. The minimum that the PCICLK clocks are enabled (PCI_STOP#
high pulse) is at least 10 PCICLK clocks. PCICLK clocks are stopped in a low state and started with a full high pulse width
guaranteed. PCICLK clock on latency cycles are only one rising PCICLK clock off latency is one PCICLK clock.
Notes:
1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9248-135 device.)
2. PCI_STOP# is an asynchronous input, and metastable conditions may exist. This signal is required to be synchronized
inside the ICS9248-135.
3. All other clocks continue to run undisturbed.
4. CPU_STOP# is shown in a high (true) state.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ICS9248YF-138 | 制造商:ICS 制造商全称:ICS 功能描述:Frequency Generator & Integrated Buffers for Celeron & PII/III⑩ |
| ICS9248YF-141-T | 制造商:ICS 制造商全称:ICS 功能描述:AMD - K7⑩ System Clock Chip |
| ICS9248YF-146-T | 制造商:ICS 制造商全称:ICS 功能描述:Frequency Generator & Integrated Buffers for Celeron & PII/III⑩ |
| ICS9248YF-157-T | 制造商:ICS 制造商全称:ICS 功能描述:Frequency Timing Generator for Pentium II Systems |
| ICS9248YF-163-T | 制造商:ICS 制造商全称:ICS 功能描述:AMD - K7⑩ System Clock Chip |
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