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参数资料
| 型号： | ICS9248YF-135-T |
| 元件分类： | XO, clock |
| 英文描述： | 150 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封装： | 0.300 INCH, SSOP-48 |
| 文件页数： | 2/15页 |
| 文件大小： | 191K |
| 代理商： | ICS9248YF-135-T |
10
ICS9248-135
Third party brands and names are the property of their respective owners.
SDRAM_STOP# Timing Diagram
Notes:
1. All timing is referenced to the internal CPU clock.
2. SDRAM is an asynchronous input and metastable conditions may exist. This signal is synchronized to the
SDRAM clocks inside the ICS9248-135.
3. All other clocks continue to run undisturbed.
SDRAM_STOP# is an asychronous input to the clock synthesizer. It is used to stop SDRAM clocks for low power operation.
SDRAM_STOP# is synchronized to complete it's current cycle, by the ICS9248-135. All other clocks will continue to run
while the SDRAM clocks are disabled. The SDRAM clocks will always be stopped in a low state and start in such a manner
that guarantees the high pulse width is a full pulse.
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相关代理商/技术参数 |
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| ICS9248YF-138 | 制造商:ICS 制造商全称:ICS 功能描述:Frequency Generator & Integrated Buffers for Celeron & PII/III⑩ |
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| ICS9248YF-157-T | 制造商:ICS 制造商全称:ICS 功能描述:Frequency Timing Generator for Pentium II Systems |
| ICS9248YF-163-T | 制造商:ICS 制造商全称:ICS 功能描述:AMD - K7⑩ System Clock Chip |
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