参数资料
型号: ICS9248YF-189-T
厂商: INTEGRATED DEVICE TECHNOLOGY INC
元件分类: 时钟产生/分配
英文描述: 133.33 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48
封装: 0.300 INCH, SSOP-48
文件页数: 10/15页
文件大小: 236K
代理商: ICS9248YF-189-T
4
ICS9248-189
Advance Information
Third party brands and names are the property of their respective owners.
Byte 1: CPU, Active/Inactive Register
(1= enable, 0 = disable)
T
I
B#
N
I
PD
W
PN
O
I
T
P
I
R
C
S
E
D
7
t
i
B8
30
#
P
O
T
S
_
K
L
C
)
#
P
O
T
S
_
K
L
C
=
0
,
#
D
P
=
1
(
6
t
i
B4
0
2
S
F
5
t
i
B5
0
1
S
F
4
t
i
B2
20
0
S
F
3
t
i
B-
0
y
c
n
e
u
q
e
r
F
e
r
a
w
t
f
o
S
/
e
r
a
w
d
r
a
H
n
o
i
t
c
e
l
e
s
2
t
i
B-
1
d
e
v
r
e
s
e
R
1
t
i
B6
40
3
S
F
0
t
i
B-
0
d
e
v
r
e
s
e
R
Byte 2: PCI, Active/Inactive Register
(1= enable, 0 = disable)
T
I
B#
N
I
PD
W
PN
O
I
T
P
I
R
C
S
E
D
7
t
i
B5
11
6
K
L
C
I
C
P
6
t
i
B2
11
5
K
L
C
I
C
P
5
t
i
B1
11
4
K
L
C
I
C
P
4
t
i
B0
11
3
K
L
C
I
C
P
3
t
i
B9
1
2
K
L
C
I
C
P
2
t
i
B8
1
K
L
C
I
C
P
1
t
i
B5
1
0
K
L
C
I
C
P
0
t
i
B4
1
F
_
K
L
C
I
C
P
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
2. Latched Frequency Selects (FS#) will be inverted logic
load of the input frequency select pin conditions.
T
I
B#
N
I
PD
W
PN
O
I
T
P
I
R
C
S
E
D
7
t
i
B-
0
d
e
v
r
e
s
e
R
6
t
i
B-
0
d
e
v
r
e
s
e
R
5
t
i
B-
0
d
e
v
r
e
s
e
R
4
t
i
B-
0
d
e
v
r
e
s
e
R
3
t
i
B-
0
d
e
v
r
e
s
e
R
2
t
i
B-
0
d
e
v
r
e
s
e
R
1
t
i
B-
0
d
e
v
r
e
s
e
R
0
t
i
B-
0
d
e
v
r
e
s
e
R
Byte 4: Peripheral , Active/Inactive Register
(1= enable, 0 = disable)
T
I
B#
N
I
PD
W
PN
O
I
T
P
I
R
C
S
E
D
7
t
i
B2
2X
)
k
c
a
b
d
a
e
r
(
0
S
F
6
t
i
B5
X
)
k
c
a
b
d
a
e
r
(
1
S
F
5
t
i
B4
X
)
k
c
a
b
d
a
e
r
(
2
S
F
4
t
i
B6
4X
)
k
c
a
b
d
a
e
r
(
3
S
F
3
t
i
B3
2X
)
k
c
a
b
d
a
e
r
(
#
8
4
_
4
2
L
E
S
2
t
i
B6
41
2
F
E
R
1
t
i
B7
41
1
F
E
R
0
t
i
B8
41
0
F
E
R
Byte 5: Peripheral , Active/Inactive Register
(1= enable, 0 = disable)
Byte 3: SDRAM, Active/Inactive Register
(1= enable, 0 = disable)
T
I
B#
N
I
PD
W
PN
O
I
T
P
I
R
C
S
E
D
7
t
i
B-
0
d
e
v
r
e
s
e
R
6
t
i
B3
20
#
8
4
_
4
2
L
E
S
5
t
i
B2
21
z
H
M
8
4
t
i
B3
21
z
H
M
8
4
_
4
2
3
t
i
B7
21
F
_
M
A
R
D
S
2
t
i
B9
2
,
8
21
)
4
:
5
(
M
A
R
D
S
1
t
i
B3
3
,
2
31
)
2
:
3
(
M
A
R
D
S
0
t
i
B7
3
,
6
31
)
0
:
1
(
M
A
R
D
S
Byte 0: CPU, Active/Inactive Register
(1= enable, 0 = disable)
T
I
B#
N
I
PD
W
PN
O
I
T
P
I
R
C
S
E
D
7
t
i
B-
0
d
e
v
r
e
s
e
R
6
t
i
B-
0
d
e
v
r
e
s
e
R
5
t
i
B-
0
d
e
v
r
e
s
e
R
4
t
i
B-
0
d
e
v
r
e
s
e
R
3
t
i
B1
4
,
0
41
0
T
/
0
C
K
L
C
U
P
C
)
X
5
.
1
=
0
,
X
1
=
1
(
2
t
i
B2
41
S
C
_
K
L
C
U
P
C
1
t
i
B1
41
0
T
K
L
C
U
P
C
0
t
i
B0
41
0
C
K
L
C
U
P
C
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