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参数资料
| 型号： | ICS9248YF-87LF |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 150 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封装： | 0.300 INCH, SSOP-48 |
| 文件页数： | 13/13页 |
| 文件大小： | 362K |
| 代理商： | ICS9248YF-87LF |
9
ICS9248-87
Preliminary Product Preview
Third party brands and names are the property of their respective owners.
Absolute Maximum Ratings
Core Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . 4.6 V
I/O Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . 3.6V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND 0.5 V to VDD +0.5 V
Ambient Operating Temperature . . . . . . . . . . . . . 0°C to +70°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . 65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = 3.3 V +5%, VDDL=2.5 V+ 5%(unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Input High Voltage
VIH
2VDD+0.3
V
Input Low Voltage
VIL
VSS-0.3
0.8
V
Input High Current
IIH
VIN = VDD
-5
5
A
Input Low Current
IIL1
VIN = 0 V; Inputs with no pull-up resistors
-5
2.0
A
Input Low Current
IIL2
VIN = 0 V; Inputs with pull-up resistors
-200
-100
A
Operating
IDD3.3OP
CL = 0 pF; Select @ 66M
60
100
mA
Supply Current
Power Down
IDD3.3PD
CL = 0 pF; With input address to Vdd or GND
400
600
A
Supply Current
Input frequency
Fi
VDD = 3.3 V;
14.318
MHz
Pin Inductance
Lpin
7nH
CIN
Logic Inputs
5
pF
Cout
Out put pin capacitance
6
pF
CINX
X1 & X2 pins
27
45
pF
Transition Time
1
Ttrans
To 1st crossing of target Freq.
3
mS
Settling Time
1
Ts
From 1st crossing to 1% target Freq.
3
mS
Clk Stabilization
1
TSTAB
From VDD = 3.3 V to 1% target Freq.
3
mS
Delay
tPZH,tPZH
output enable delay (all outputs)
1
10
nS
tPLZ,tPZH
output disable delay (all outputs)
1
10
nS
1Guarenteed by design, not 100% tested in production.
Input Capacitance
1
p
u
o
r
G
z
H
M
6
U
P
Cz
H
M
0
1
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P
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.
0s
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0
5
6
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t
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n
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7s
p
0
5s
n
0
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5s
p
0
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.
0s
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0
5
6
V
3
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t
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n
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.
0s
p
0
5s
n
0
.
0s
p
0
5s
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0s
p
0
5
I
C
P
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6
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3s
n
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3
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5
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p
0
5s
n
5
.
3
-
5
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1s
p
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5
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3
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5
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5
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I
C
Ps
n
0
.
0s
n
0
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1s
n
0
.
0s
n
0
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1s
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0
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0s
n
0
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1
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AA
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AA
/
N
Group Timing Relationship Table
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