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参数资料
| 型号： | ICS9248YF-87LF |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 150 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封装： | 0.300 INCH, SSOP-48 |
| 文件页数： | 9/13页 |
| 文件大小： | 362K |
| 代理商： | ICS9248YF-87LF |
5
ICS9248-87
Preliminary Product Preview
Third party brands and names are the property of their respective owners.
Byte 0: Control Register Active/Inactive Register
(1= enable, 0 = disable)
T
I
B#
N
I
PD
W
PN
O
I
T
P
I
R
C
S
E
D
7
t
i
B-
0
d
e
v
r
e
s
e
R
6
t
i
B-
0
d
e
v
r
e
s
e
R
5
t
i
B-
0
d
e
v
r
e
s
e
R
4
t
i
B-
0
d
e
v
r
e
s
e
R
3
t
i
B-
0
d
e
v
r
e
s
e
R
2
t
i
B3
21
z
H
M
8
4
/
4
2
1
t
i
B2
2
,
1
21
z
H
M
8
4
0
t
i
B-
0
d
e
v
r
e
s
e
R
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
2. Latched Frequency Selects (FS#) will be inverted logic
load of the input frequency select pin conditions.
3. SDRAM_F is free running and cannot be turned off by I2C
Byte 5: Peripheral , Active/Inactive Register
(1= enable, 0 = disable)
T
I
B#
N
I
PD
W
PN
O
I
T
P
I
R
C
S
E
D
7
t
i
B-
0
d
e
v
r
e
s
e
R
6
t
i
B-
0
d
e
v
r
e
s
e
R
5
t
i
B-
0
d
e
v
r
e
s
e
R
4
t
i
B-
0
d
e
v
r
e
s
e
R
3
t
i
B-
0
d
e
v
r
e
s
e
R
2
t
i
B-
0
d
e
v
r
e
s
e
R
1
t
i
B-
0
d
e
v
r
e
s
e
R
0
t
i
B-
0
d
e
v
r
e
s
e
R
T
I
B#
N
I
PD
W
PN
O
I
T
P
I
R
C
S
E
D
7
t
i
B-
0
)
e
t
o
N
(
d
e
v
r
e
s
e
R
6
t
i
B-
0
)
e
t
o
N
(
d
e
v
r
e
s
e
R
5
t
i
B-
0
)
e
t
o
N
(
d
e
v
r
e
s
e
R
4
t
i
B-
0
)
e
t
o
N
(
d
e
v
r
e
s
e
R
3
t
i
B-
0
)
e
t
o
N
(
d
e
v
r
e
s
e
R
2
t
i
B-
1
)
e
t
o
N
(
d
e
v
r
e
s
e
R
1
t
i
B-
1
)
e
t
o
N
(
d
e
v
r
e
s
e
R
0
t
i
B-
0
)
e
t
o
N
(
d
e
v
r
e
s
e
R
Byte 6: Peripheral , Active/Inactive Register
(1= enable, 0 = disable)
Note: Dont write into this register, writing into this
register can cause malfunction
Byte 2: PCI, Active/Inactive Register
(1= enable, 0 = disable)
T
I
B#
N
I
PD
W
PN
O
I
T
P
I
R
C
S
E
D
7
t
i
B9
11
7
K
L
C
I
C
P
6
t
i
B8
11
6
K
L
C
I
C
P
5
t
i
B7
11
5
K
L
C
I
C
P
4
t
i
B5
11
4
K
L
C
I
C
P
3
t
i
B4
11
3
K
L
C
I
C
P
2
t
i
B2
11
2
K
L
C
I
C
P
1
t
i
B1
11
1
K
L
C
I
C
P
0
t
i
B0
11
0
K
L
C
I
C
P
Byte 3: Reserved , Active/Inactive Register
(1= enable, 0 = disable)
Byte 1: SDRAM, Active/Inactive Register
(1= enable, 0 = disable)
T
I
B#
N
I
PD
W
PN
O
I
T
P
I
R
C
S
E
D
7
t
i
B2
31
7
M
A
R
D
S
6
t
i
B3
31
6
M
A
R
D
S
5
t
i
B5
31
5
M
A
R
D
S
4
t
i
B6
31
4
M
A
R
D
S
3
t
i
B7
31
3
M
A
R
D
S
2
t
i
B9
31
2
M
A
R
D
S
1
t
i
B0
41
1
M
A
R
D
S
0
t
i
B1
41
0
M
A
R
D
S
T
I
B#
N
I
PD
W
PN
O
I
T
P
I
R
C
S
E
D
7
t
i
B-
0
d
e
v
r
e
s
e
R
6
t
i
B-
X
#
2
S
F
5
t
i
B-
X
#
1
S
F
4
t
i
B-
X
#
0
S
F
3
t
i
B-
1
C
I
P
A
O
I
2
t
i
B-
X
#
)
#
8
4
_
4
2
L
E
S
(
1
t
i
B-
1
C
I
P
A
O
I
_
Q
E
R
F
2
/
K
L
C
I
C
P
=
C
I
P
A
O
I
>
=
1
=
>
=
0
=
C
I
P
A
O
I
_
Q
E
R
F
K
L
C
I
C
P
=
C
I
P
A
O
I
0
t
i
B-
X
#
3
S
F
相关PDF资料 |
PDF描述 |
|---|---|
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| ICS9248YF-95LF | 124 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| ICS9248YF-96LF-T | 150 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ICS9248YF-90-T | 制造商:ICS 制造商全称:ICS 功能描述:Frequency Generator & Integrated Buffers for PENTIUM/ProTM |
| ICS9248YF-96LF-T | 制造商:ICS 制造商全称:ICS 功能描述:Frequency Generator & Integrated Buffers for Celeron & PII/III⑩ |
| ICS9248YF-96-T | 制造商:ICS 制造商全称:ICS 功能描述:Frequency Generator & Integrated Buffers for Celeron & PII/III⑩ |
| ICS9248YF-97-T | 制造商:ICS 制造商全称:ICS 功能描述:Frequency Timing Generator for PENTIUM II Systems |
| ICS9248YF-98-T | 制造商:ICS 制造商全称:ICS 功能描述:Frequency Generator & Integrated Buffers for Celeron & PII/III⑩ |
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