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参数资料
| 型号： | ICS9248YF-90LF-T |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 132.99 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封装： | 0.300 INCH, SSOP-48 |
| 文件页数： | 5/16页 |
| 文件大小： | 281K |
| 代理商： | ICS9248YF-90LF-T |
13
ICS9248- 90
CPU_STOP# Timing Diagram
CPU_STOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPU clocks for low power operation.
CPU_STOP# is synchronized by the ICS9248-90. The minimum that the CPU clock is enabled (CPU_STOP# high pulse) is
100 CPU clocks. All other clocks will continue to run while the CPU clocks are disabled. The CPU clocks will always be
stopped in a low state and start in such a manner that guarantees the high pulse width is a full pulse. CPU clock on latency is
less than 4 CPU clocks and CPU clock off latency is less than 4 CPU clocks.
Notes:
1. All timing is referenced to the internal CPU clock.
2. CPU_STOP# is an asynchronous input and metastable conditions may exist. This signal is synchronized
to the CPU clocks inside the ICS9248-90.
3. IOAPIC output is Stopped Glitch Free by CPUSTOP# going low.
4. SDRAM-F output is controlled by Buffer in signal, not affected by the ICS9248-90
CPU_STOP# signal. SDRAM (0:11) are controlled as shown.
5. All other clocks continue to run undisturbed.
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| ICS9248YF-90LF | 132.99 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| ICS9248YF-95LF | 124 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| ICS9248YF-96LF-T | 150 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ICS9248YF-90-T | 制造商:ICS 制造商全称:ICS 功能描述:Frequency Generator & Integrated Buffers for PENTIUM/ProTM |
| ICS9248YF-96LF-T | 制造商:ICS 制造商全称:ICS 功能描述:Frequency Generator & Integrated Buffers for Celeron & PII/III⑩ |
| ICS9248YF-96-T | 制造商:ICS 制造商全称:ICS 功能描述:Frequency Generator & Integrated Buffers for Celeron & PII/III⑩ |
| ICS9248YF-97-T | 制造商:ICS 制造商全称:ICS 功能描述:Frequency Timing Generator for PENTIUM II Systems |
| ICS9248YF-98-T | 制造商:ICS 制造商全称:ICS 功能描述:Frequency Generator & Integrated Buffers for Celeron & PII/III⑩ |
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