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参数资料
| 型号： | ICS9248YG-171-T |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 133.33 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封装： | 6.10 MM, 0.50 MM PITCH, TSSOP-48 |
| 文件页数： | 4/15页 |
| 文件大小： | 209K |
| 代理商： | ICS9248YG-171-T |
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ICS9248-171
Advance Information
Third party brands and names are the property of their respective owners.
PCI_STOP# Timing Diagram
PCI_STOP# is an asynchronous input to the ICS9248-171. It is used to turn off the PCICLK clocks for low power operation.
PCI_STOP# is synchronized by the ICS9248-171 internally. The minimum that the PCICLK clocks are enabled (PCI_STOP#
high pulse) is at least 10 PCICLK clocks. PCICLK clocks are stopped in a low state and started with a full high pulse width
guaranteed. PCICLK clock on latency cycles are only one rising PCICLK clock off latency is one PCICLK clock.
Notes:
1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9248-171 device.)
2. PCI_STOP# is an asynchronous input, and metastable conditions may exist. This signal is required to be synchronized
inside the ICS9248-171.
3. All other clocks continue to run undisturbed.
4. CPU_STOP# is shown in a high (true) state.
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| ICS9248YG-192-T | 制造商:ICS 制造商全称:ICS 功能描述:Frequency Timing Generator for Transmeta Systems |
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