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参数资料
| 型号： | ICS9248YG-171-T |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 133.33 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封装： | 6.10 MM, 0.50 MM PITCH, TSSOP-48 |
| 文件页数： | 8/15页 |
| 文件大小： | 209K |
| 代理商： | ICS9248YG-171-T |
2
ICS9248-171
Advance Information
Third party brands and names are the property of their respective owners.
Pin Descriptions
Notes:
1:
Internal Pull-up Resistor of 120K to 3.3V on indicated inputs
2:
Internal pull-down resistor of 120K to GND.
3:
Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use 10Kohm resistor
to program logic Hi to VDD or GND for logic low.
PIN NUMBER
PIN NAME
TYPE
DESCRIPTION
1
DG_STOP#
1
IN
DG_STOP halts SDRAM and/or AGP clocks at logic "0" when driven low.
The stops selection can be programed through I
2C.
2
PD#
1
IN
Asynchronous active low input pin used to power down the device into a low
power state. The internal clocks are disabled and the VCO and the crystal are
stopped. The latency of the power down will not be greater than 3ms.
4
X1
IN
Crystal input,nominally 14.318M Hz.
5
X2
OUT
Crystal output, nominally 14.318MHz.
3, 11, 16, 23, 29,
34, 41, 48
GND
PWR
Ground pins
8, 17, 28, 35, 40
VDD
PWR
Power supply pins, nominal 3.3V
6
AVDD
PWR
Analog power supply pin, nominal 3.3V
FS0
2, 3
IN
Frequency select pin.
REF0
OUT
14.318 M Hz reference clock.
FS1
2, 3
IN
Frequency select pin.
AGP0
OUT
AGP outputs defined as 2X PCI. These may not be stopped.
10
AGP1
OUT
AGP outputs defined as 2X PCI. These may not be stopped.
PCICLK_F
OUT
Free running PCICLK not stoped by PCI_STOP#
FS2
1, 3
IN
Frequency select pin.
20, 19, 15, 14, 13
PCICLK
(5:4) (2:0)
OUT
PCI clock outputs.
PCICLK3
OUT
PCI clock output.
MODE
1, 3
IN
Function select pin, 1=Desktop M ode, 0=M obile M ode.
21
AVDD48
PWR
Analog power supply pin, nominal 3.3V
FS3
2, 3
IN
Frequency select pin.
48MHz
OUT
48MHz output clock
24
SCLK
IN
Clock input of I
2C input, 5V tolerant input
PCI_STOP#
1
IN
Stops all PCICLKs besides the PCICLK_F clocks at logic 0 level,
when input low
SDRAM 10
OUT
SDRAM clock output.
25, 26, 30, 31, 32,
33, 36, 37, 38, 39,
42, 43
SDRAM
(12:11, 9:0 )
OUT
SDRAM clock outputs.
44
SDATA
I/O
Data pin for I
2C circuitry 5V tolerant
45, 47
CPUCLKT (1:0)
OUT
"True" clocks of differential pair CPU outputs. These open drain outputs
need an external 1.5V pull-up.
46
CPUCLKC0
OUT
"Complementory" clocks of differential pair CPU outputs. This open drain
output need an external 1.5V pull-up.
9
7
27
12
22
18
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