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参数资料
| 型号： | ICS9248YG-185LF-T |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 133.33 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO28 |
| 封装： | 4.40 MM, 0.65 MM PITCH, TSSOP-28 |
| 文件页数： | 10/11页 |
| 文件大小： | 100K |
| 代理商： | ICS9248YG-185LF-T |
8
ICS9248- 185
PCI_STOP# Timing Diagram
PCI_STOP# is an asynchronous input to the ICS9248-185. It is used to turn off the PCICLK clocks for low power operation.
PCI_STOP# is synchronized by the ICS9248-185 internally. The minimum that the PCICLK clocks are enabled (PCI_STOP#
high pulse) is at least 10 PCICLK clocks. PCICLK clocks are stopped in a low state and started with a full high pulse width
guaranteed. PCICLK clock on latency cycles are only three rising PCICLK clocks, off latency is one PCICLK clock.
Notes:
1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9248 device.)
2. PCI_STOP# is an asynchronous input, and metastable conditions may exist. This signal is required to be synchronized
inside the ICS9248.
3. All other clocks continue to run undisturbed.
4. CLK_STOP# is shown in a high (true) state.
CPUCLK
(Internal)
PCICLK_F
(Internal)
PCICLK_F
(Free-running)
CLK_STOP#
PCICLK [6:0]
PCI_STOP#
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相关代理商/技术参数 |
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| ICS9248YG-192-T | 制造商:ICS 制造商全称:ICS 功能描述:Frequency Timing Generator for Transmeta Systems |
| ICS9248YG-195LF-T | 制造商:ICS 制造商全称:ICS 功能描述:Frequency Generator & Integrated Buffers for PENTIUM II/III & K6 |
| ICS9248YG-50 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Peripheral IC |
| ICS9248YG-50T | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Peripheral IC |
| ICS9248YG-50-T | 制造商:ICS 制造商全称:ICS 功能描述:Frequency Timing Generator for Pentium II Systems |
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