- 您现在的位置：买卖IC网 > PDF目录69002 > ICS9248YG-50LF-T (INTEGRATED DEVICE TECHNOLOGY INC) 100 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO28 PDF资料下载
参数资料
| 型号： | ICS9248YG-50LF-T |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 100 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO28 |
| 封装： | 6.10 MM, 0.65 MM PITCH, TSSOP-28 |
| 文件页数： | 5/11页 |
| 文件大小： | 261K |
| 代理商： | ICS9248YG-50LF-T |
3
ICS9248-50
Select Functions
(Functionality determined by TS# and SEL100/66# pin, see below)
Notes:
1. TCLK is a test clock driven on the X1 (crystal in pin) input during test mode.
y
t
i
l
a
n
o
i
t
c
n
u
FK
L
C
U
P
C
,
I
C
P
F
_
I
C
P
0
F
E
R
e
t
a
t
s
i
r
TZ
-
I
HZ
-
I
HZ
-
I
H
e
d
o
m
t
s
e
T2
/
K
L
C
T
1
6
/
K
L
C
T
1
K
L
C
T
1
#
6
/
0
1
L
E
S#
S
Tn
o
i
t
c
n
u
F
00
e
t
a
t
S
-
i
r
T
0-
)
d
e
v
r
e
s
e
R
(
0-
)
d
e
v
r
e
s
e
R
(
01
I
C
P
3
.
3
,
U
P
C
z
H
M
6
.
6
e
v
i
t
c
A
10
e
d
o
M
t
s
e
T
1-
)
d
e
v
r
e
s
e
R
(
1-
)
d
e
v
r
e
s
e
R
(
11
I
C
P
3
.
3
,
U
P
C
z
H
M
0
1
e
v
i
t
c
A
Power Management
ICS9248-50 Power Management Requirements
Clock Enable Configuration
Full clock cycle timing is guaranteed at all times after the system has initially powered up except where noted. During power
up and power down operations using the PD# pin will not cause clocks of a short or longer pulse than that of the running
clock. The first clock pulse coming out of a stopped clock condition may be slightly distorted due to clock network charging
circuitry. Board routing and signal loading may have a large impact on the initial clock distortion also.
Notes.
1. Clock on latency is defined from when the clock enable goes active to when the first valid clock comes out of the device.
2. Clock off latency is defined from when the clock enable goes inactive to when the last clock is driven low out of the device.
3. Power up latency is when PD# goes inactive (high) to when the first valid clocks are output by the device.
4. Power down has controlled clock counts applicable to CPUCLK, PCICLK only.
The REF will be stopped independant of these.
L
A
N
G
I
SE
T
A
T
S
L
A
N
G
I
S
y
c
n
e
t
a
L
g
n
i
n
u
r
e
r
f
o
s
e
g
d
e
g
n
i
s
i
r
f
o
.
o
N
K
L
C
I
C
P
#
P
O
T
S
_
U
P
C)
d
e
l
b
a
s
i
D
(
0
2
1
)
d
e
l
b
a
n
E
(
1
#
P
O
T
S
_
I
C
P)
d
e
l
b
a
s
i
D
(
0
2
1
)
d
e
l
b
a
n
E
(
1
#
D
P)
n
o
i
t
a
r
e
p
O
l
a
m
r
o
N
(
1
3
s
m
3
)
n
w
o
D
r
e
w
o
P
(
0
4
x
a
m
2
#
P
O
T
S
_
U
P
C#
P
O
T
S
_
I
C
P#
N
W
D
_
R
W
PK
L
C
U
P
CK
L
C
I
C
PF
_
K
L
C
I
C
PF
E
Rl
a
t
s
y
r
Cs
O
C
V
XX
0
w
o
Lw
o
Lw
o
Ld
e
p
o
t
Sf
f
Of
f
O
00
1
w
o
Lw
o
Lz
H
M
3
.
3
3g
n
i
n
u
Rg
n
i
n
u
Rg
n
i
n
u
R
01
1
w
o
Lz
H
M
3
.
3
3z
H
M
3
.
3
3g
n
i
n
u
Rg
n
i
n
u
Rg
n
i
n
u
R
10
1
z
H
M
6
.
6
/
0
1w
o
Lz
H
M
3
.
3
3g
n
i
n
u
Rg
n
i
n
u
Rg
n
i
n
u
R
11
1
z
H
M
6
.
6
/
0
1z
H
M
3
.
3
3z
H
M
3
.
3
3g
n
i
n
u
Rg
n
i
n
u
Rg
n
i
n
u
R
相关PDF资料 |
PDF描述 |
|---|---|
| ICS9DB306BLLFT | 9DB SERIES, PLL BASED CLOCK DRIVER, 6 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO28 |
| ICS9DB306BFLF | 9DB SERIES, PLL BASED CLOCK DRIVER, 6 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO28 |
| ICSSSTU32864YHT | SSTU SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PBGA96 |
| IDT5T2110NLGI8 | 5T SERIES, PLL BASED CLOCK DRIVER, 5 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQCC68 |
| IDT5T9306PFI | LOW SKEW CLOCK DRIVER, 6 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ICS9248YG-50T | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Peripheral IC |
| ICS9248YG-50-T | 制造商:ICS 制造商全称:ICS 功能描述:Frequency Timing Generator for Pentium II Systems |
| ICS9248YG-56-T | 制造商:ICS 制造商全称:ICS 功能描述:Frequency Timing Generator for Pentium II Systems |
| ICS9248YG-92 | 制造商:ICS 制造商全称:ICS 功能描述:Mobile Pentium IITM System Clock Chip |
| ICS9250-08 | 制造商:ICS 制造商全称:ICS 功能描述:Frequency Generator & Integrated Buffers for Celeron & PII/III⑩ |
发布紧急采购，3分钟左右您将得到回复。