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参数资料
| 型号： | ICS9248YG-92 |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 100 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封装： | 6.10 MM, 0.50 MM PITCH, TSSOP-48 |
| 文件页数： | 11/14页 |
| 文件大小： | 341K |
| 代理商： | ICS9248YG-92 |
6
ICS9248-92
Byte 5: Peripheral Clock Register
Notes: 1 = Enabled; 0 = Disabled, outputs held low
T
I
B#
N
I
PD
W
PN
O
I
T
P
I
R
C
S
E
D
7
t
i
B-
1
d
e
v
r
e
s
e
R
6
t
i
B-
1
d
e
v
r
e
s
e
R
5
t
i
B-
1
d
e
v
r
e
s
e
R
4
t
i
B-
1
d
e
v
r
e
s
e
R
3
t
i
B-
1
d
e
v
r
e
s
e
R
2
t
i
B5
41
)
t
c
a
n
I
/
t
c
A
(
2
F
E
R
1
t
i
B1
1
)
t
c
a
n
I
/
t
c
A
(
1
F
E
R
0
t
i
B2
1
)
t
c
a
n
I
/
t
c
A
(
0
F
E
R
PWD = Power-Up Default
Byte 6: Optional Register for Future
Notes:
1. Byte 6 is reserved by Integrated Circuit Systems for
future applications.
T
I
B#
N
I
PD
W
PN
O
I
T
P
I
R
C
S
E
D
7
t
i
B-
1
d
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v
r
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s
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R
6
t
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B-
1
d
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v
r
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R
5
t
i
B-
1
d
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v
r
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s
e
R
4
t
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B-
1
d
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v
r
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s
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R
3
t
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B-
1
d
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v
r
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s
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R
2
t
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B-
1
d
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v
r
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s
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R
1
t
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B-
1
d
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v
r
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s
e
R
0
t
i
B-
1
d
e
v
r
e
s
e
R
Byte 1: CPU, 24/48 MHz Clock Register
Notes: 1 = Enabled; 0 = Disabled, outputs held low
Byte 2: PCICLK Clock Register
Byte 4: SDRAM Clock Register
Notes: 1 = Enabled; 0 = Disabled, outputs held low
T
I
B#
N
I
PD
W
PN
O
I
T
P
I
R
C
S
E
D
7
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B-
1
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R
6
t
i
B8
1
)
t
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I
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A
(
F
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K
L
C
I
C
P
5
t
i
B6
11
)
t
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a
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I
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A
(
5
K
L
C
I
C
P
4
t
i
B4
11
)
t
c
a
n
I
/
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A
(
4
K
L
C
I
C
P
3
t
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B3
11
)
t
c
a
n
I
/
t
c
A
(
3
K
L
C
I
C
P
2
t
i
B2
11
)
t
c
a
n
I
/
t
c
A
(
2
K
L
C
I
C
P
1
t
i
B1
11
)
t
c
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n
I
/
t
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A
(
1
K
L
C
I
C
P
0
t
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B9
1
)
t
c
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n
I
/
t
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A
(
0
K
L
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I
C
P
T
I
B#
N
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W
PN
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I
T
P
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D
7
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B-
1
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v
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R
6
t
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B-
1
d
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v
r
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s
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R
5
t
i
B-
1
d
e
v
r
e
s
e
R
4
t
i
B-
1
d
e
v
r
e
s
e
R
3
t
i
B-
1
d
e
v
r
e
s
e
R
2
t
i
B-
1
d
e
v
r
e
s
e
R
1
t
i
B-
1
d
e
v
r
e
s
e
R
0
t
i
B-
1
d
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v
r
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s
e
R
T
I
B#
N
I
PD
W
PN
O
I
T
P
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R
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S
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D
7
t
i
B3
21
)
t
c
a
n
I
/
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A
(
z
H
M
4
2
/
8
4
6
t
i
B2
21
)
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H
M
4
2
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8
4
5
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1
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4
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3
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1
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2
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1
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1
t
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B1
41
)
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A
(
1
K
L
C
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P
C
0
t
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B2
41
)
t
c
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n
I
/
t
c
A
(
0
K
L
C
U
P
C
Byte 3: SDRAM Clock Register
Notes: 1 = Enabled; 0 = Disabled, outputs held low
T
I
B#
N
I
PD
W
PN
O
I
T
P
I
R
C
S
E
D
7
t
i
B6
21
)
t
c
a
n
I
/
t
c
A
(
7
M
A
R
D
S
6
t
i
B7
21
)
t
c
a
n
I
/
t
c
A
(
6
M
A
R
D
S
5
t
i
B9
21
)
t
c
a
n
I
/
t
c
A
(
5
M
A
R
D
S
4
t
i
B0
31
)
t
c
a
n
I
/
t
c
A
(
4
M
A
R
D
S
3
t
i
B2
31
)
t
c
a
n
I
/
t
c
A
(
3
M
A
R
D
S
2
t
i
B3
31
)
t
c
a
n
I
/
t
c
A
(
2
M
A
R
D
S
1
t
i
B5
31
)
t
c
a
n
I
/
t
c
A
(
1
M
A
R
D
S
0
t
i
B6
31
)
t
c
a
n
I
/
t
c
A
(
0
M
A
R
D
S
Note: PWD = Power-Up Default
相关PDF资料 |
PDF描述 |
|---|---|
| ICS9250YF-08 | 150 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56 |
| ICS9250YF-08LF | 150 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56 |
| ICS9250YF-08LF | 150 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56 |
| ICS9250YF-14-T | 149.69 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56 |
| ICS9250YF-PPP-T | 149.69 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ICS9250-08 | 制造商:ICS 制造商全称:ICS 功能描述:Frequency Generator & Integrated Buffers for Celeron & PII/III⑩ |
| ICS9250-09 | 制造商:ICS 制造商全称:ICS 功能描述:Frequency Timing Generator for PENTIUM II Systems |
| ICS9250-10 | 制造商:ICS 制造商全称:ICS 功能描述:Frequency Timing Generator for Pentium II Systems |
| ICS9250-11 | 制造商:ICS 制造商全称:ICS 功能描述:Frequency Timing Generator for PENTIUM II/III Systems |
| ICS9250-12 | 制造商:ICS 制造商全称:ICS 功能描述:Frequency Timing Generator for PENTIUM II/III Systems |
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