- 您现在的位置：买卖IC网 > PDF目录1999 > ICS932S200BG (IDT, Integrated Device Technology Inc)IC FREQ TIMING GENERATOR 56TSSOP PDF资料下载
参数资料
| 型号： | ICS932S200BG |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 10/13页 |
| 文件大小： | 0K |
| 描述： | IC FREQ TIMING GENERATOR 56TSSOP |
| 标准包装： | 34 |
| 类型： | 时钟/频率发生器 |
| PLL： | 是 |
| 主要目的： | 服务器 |
| 输入： | 晶体 |
| 输出： | 时钟 |
| 电路数： | 1 |
| 比率 - 输入:输出： | 1:20 |
| 差分 - 输入:输出： | 无/无 |
| 频率 - 最大： | 133MHz |
| 电源电压： | 3.135 V ~ 3.465 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 56-TFSOP（0.240"，6.10mm 宽） |
| 供应商设备封装： | 56-TSSOP |
| 包装： | 管件 |
| 其它名称： | 932S200BG |
6
ICS932S200
0427D—12/15/08
PD# Timing Diagram
The power down selection is used to put the part into a very low power state without turning off the power to the part.
PD# is an asynchronous active low input.This signal needs to be synchronized internal to the device prior to powering
down the clock synthesizer.
Internal clocks are not running after the device is put in power down.When PD# is active low all clocks need to be driven
to a low value and held prior to turning off the VCOs and crystal. The power up latency needs to be less than 3 mS.
The power down latency should be as short as possible but conforming to the sequence requirements shown below.
PCI_STOP# and CPU_STOP# are considered to be don't cares during the power down operations.The REF and 48MHz
clocks are expected to be stopped in the LOW state as soon as possible. Due to the state of the internal logic, stopping
and holding the REF clock outputs in the LOW state may require more than one clock cycle to complete.
Notes:
1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS932S200 device).
2. As shown, the outputs Stop Low on the next falling edge after PD# goes low.
3. PD# is an asynchronous input and metastable conditions may exist. This signal is synchronized inside this part.
4. The shaded sections on the VCO and the Crystal signals indicate an active clock.
5. Diagrams shown with respect to 133MHz. Similar operation when CPU is 100MHz.
CPUCLK
3V66
PCICLK
VCO
Crystal
PD#
相关PDF资料 |
PDF描述 |
|---|---|
| ICS932S203AFLN | IC FREQ GEN W/CPU CLOCK 56-SSOP |
| ICS932S431AGLF | IC CLOCK CHIP 56-TSSOP |
| ICS932S890CKLF | IC CLK CHIP EXPRESS 72MLF |
| ICS93716BGLF | IC DDR PLL CLOCK DRIVER 28-TSSOP |
| ICS94201DFLF | IC FREQ GENERATOR PROGR 56-SSOP |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ICS932S200BGT | 功能描述:IC FREQ TIMING GENERATOR 56TSSOP RoHS:否 类别:集成电路 (IC) >> 时钟/计时 - 专用 系列:- 标准包装:1,500 系列:- 类型:时钟缓冲器/驱动器 PLL:是 主要目的:- 输入:- 输出:- 电路数:- 比率 - 输入:输出:- 差分 - 输入:输出:- 频率 - 最大:- 电源电压:3.3V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:28-SSOP（0.209"，5.30mm 宽） 供应商设备封装:28-SSOP 包装:带卷 (TR) 其它名称:93786AFT |
| ICS932S200YF-T | 制造商:ICS 制造商全称:ICS 功能描述:Frequency Timing Generator for Dual Server/Workstation Systems |
| ICS932S200YG-T | 制造商:ICS 制造商全称:ICS 功能描述:Frequency Timing Generator for Dual Server/Workstation Systems |
| ICS932S202 | 制造商:ICS 制造商全称:ICS 功能描述:Frequency Timing Generator for Differential PIIIType Dual-CPU Systems |
| ICS932S203 | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:Frequency Generator with 133MHz Differential CPU Clocks |
发布紧急采购，3分钟左右您将得到回复。