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| 型号： | ICS932S200BG |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 9/13页 |
| 文件大小： | 0K |
| 描述： | IC FREQ TIMING GENERATOR 56TSSOP |
| 标准包装： | 34 |
| 类型： | 时钟/频率发生器 |
| PLL： | 是 |
| 主要目的： | 服务器 |
| 输入： | 晶体 |
| 输出： | 时钟 |
| 电路数： | 1 |
| 比率 - 输入:输出： | 1:20 |
| 差分 - 输入:输出： | 无/无 |
| 频率 - 最大： | 133MHz |
| 电源电压： | 3.135 V ~ 3.465 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 56-TFSOP（0.240"，6.10mm 宽） |
| 供应商设备封装： | 56-TSSOP |
| 包装： | 管件 |
| 其它名称： | 932S200BG |
5
ICS932S200
0427D—12/15/08
PCI_STOP# Timing Diagram
PCI_STOP# is an input to the clock synthesizer and must be made synchronous to the clock driver PCICLK_F output.
It is used to turn off the PCI clocks for low power operation. PCI clocks are required to be stopped in a low state and
started such that a full high pulse width is guaranteed. ONLY one rising edge of PCICLK_F is allowed after the clock
control logic switched for the PCI outputs to become enabled/disabled.
Notes:
1. All timing is referenced to CPUCLK.
2. Internal means inside the chip.
3. All other clocks continue to run undisturbed.
4. PD# and CPU_STOP# are shown in a high state.
5. Diagrams shown with respect to 133MHz. Similar operation when CPU is 100MHz.
CPUCLK
(internal)
(externall)
PCICLK
PCI_STOP#
CPU_STOP#
PD#
PCICLK
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相关代理商/技术参数 |
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| ICS932S200BGT | 功能描述:IC FREQ TIMING GENERATOR 56TSSOP RoHS:否 类别:集成电路 (IC) >> 时钟/计时 - 专用 系列:- 标准包装:1,500 系列:- 类型:时钟缓冲器/驱动器 PLL:是 主要目的:- 输入:- 输出:- 电路数:- 比率 - 输入:输出:- 差分 - 输入:输出:- 频率 - 最大:- 电源电压:3.3V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:28-SSOP（0.209"，5.30mm 宽） 供应商设备封装:28-SSOP 包装:带卷 (TR) 其它名称:93786AFT |
| ICS932S200YF-T | 制造商:ICS 制造商全称:ICS 功能描述:Frequency Timing Generator for Dual Server/Workstation Systems |
| ICS932S200YG-T | 制造商:ICS 制造商全称:ICS 功能描述:Frequency Timing Generator for Dual Server/Workstation Systems |
| ICS932S202 | 制造商:ICS 制造商全称:ICS 功能描述:Frequency Timing Generator for Differential PIIIType Dual-CPU Systems |
| ICS932S203 | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:Frequency Generator with 133MHz Differential CPU Clocks |
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