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参数资料
| 型号： | ICS932S200BGT |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 6/13页 |
| 文件大小： | 0K |
| 描述： | IC FREQ TIMING GENERATOR 56TSSOP |
| 标准包装： | 2,000 |
| 类型： | 时钟/频率发生器 |
| PLL： | 是 |
| 主要目的： | 服务器 |
| 输入： | 晶体 |
| 输出： | 时钟 |
| 电路数： | 1 |
| 比率 - 输入:输出： | 1:20 |
| 差分 - 输入:输出： | 无/无 |
| 频率 - 最大： | 133MHz |
| 电源电压： | 3.135 V ~ 3.465 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 56-TFSOP（0.240"，6.10mm 宽） |
| 供应商设备封装： | 56-TSSOP |
| 包装： | 带卷 (TR) |
| 其它名称： | 932S200BGT |
2
ICS932S200
0427D—12/15/08
Pin Descriptions
Pin number
Pin name
Type
Description
1, 7, 8, 13, 19
20, 21, 24, 29,
38, 40, 44, 48,
52
GND
PWR
Gnd pins
3, 2
REF(1:0)
OUT
14.318MHz reference clock outputs at 3.3V
4,. 10, 16, 17,
22, 23, 27, 31,
39
VDD
PWR
Power pins 3.3V
5
X1
IN
XTAL_IN 14.318MHz crystal input
6
X2
OUT
XTAL_OUT Crystal output
9
PCICLK_F
OUT
Free running PCI clock not affected by PCI_STOP#
18, 15, 14,
12, 11
PCICLK (4:0)
OUT
PCI clock outputs at 3.3V. Synchronous to CPU clocks.
26, 25
3V66 (1:0)
OUT
66MHz outputs at 3.3V. These outputs are stopped when CPU_STOP# is
driven active..
28
SEL 133/100#
IN
This selects the frequency for the CPU and CPU/2 outputs. High =
133MHz, Low=100MHz
30
48MHz
OUT
Fixed 48MHz clock output. 3.3V
33, 32
SEL (1:0)
IN
Function select pins. See truth table for details.
34
SPREAD#
IN
Enables spread spectrum when active(Low). modulates all the CPU, PCI,
IOAPIC and 3V66 clocks. Does not affect the REF and 48MHz clocks.
0.5% down spread modulation.
35
PD#
IN
This asynchronous input powers down the chip when drive active(Low).
The internal PLLs are disabled and all the output clocks are held at a Low
state.
36
CPU_STOP#
IN
This asychronous input halts the CPUCLK and the 3V66 clocks at logic "0"
when driven active(Low).
37
PCI_STOP#
IN
This asynchronous input halts the PCICLK at logic"0" when driven
active(Low). PCICLK_F is not affected by this input.
43, 47, 51, 56
VDDL
PWR
Power pins 2.5V
50, 49, 46,
45, 42, 41
CPUCLK (5:0)
OUT
Host bus clock output at 2.5V. 133MHz or 100MHz depending on the state
of the SEL 133/100MHz.
55, 54, 53
IOAPIC (2:0)
OUT
IOAPIC clocks at 2.5V. Synchronous with CPUCLKs but fixed at
16.67MHz.
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