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参数资料
| 型号： | ICS93732AFLF |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟及定时 |
| 英文描述： | 93732 SERIES, PLL BASED CLOCK DRIVER, 6 TRUE OUTPUT(S), 6 INVERTED OUTPUT(S), PDSO28 |
| 封装： | 0.209 INCH, GREEN, MO-150, SSOP-28 |
| 文件页数： | 8/11页 |
| 文件大小： | 126K |
| 代理商： | ICS93732AFLF |
6
ICS93732
0578I—05/18/05
Bytes 0 to 4 are reseved power up default = 1. This allows operation with main clock.
Pin #
Name
0
1
PWD
Bit 7
2, 1
DDR0(T&C)
Output Control
RW
DISABLE ENABLE
1
Bit 6
4, 5
DDR1(T&C)
Output Control
RW
DISABLE ENABLE
1
Bit 5
-
Reserved
X
-
1
Bit 4
-
Reserved
X
-
1
Bit 3
13, 14
DDR2(T&C)
Output Control
RW
DISABLE ENABLE
1
Bit 2
17, 16
DDR3(T&C)
Output Control
RW
DISABLE ENABLE
1
Bit 1
-
Reserved
X
-
1
Bit 0
-
Reserved
X
-
1
Note:
Pin #
Name
0
1
PWD
Bit 7
-
Reserved
X
-
0
Bit 6
-
Reserved
X
-
0
Bit 5
-
Reserved
X
-
0
Bit 4
-
Reserved
X
-
1
Bit 3
24, 25
DDR4(T&C)
Output Control
RW
DISABLE ENABLE
1
Bit 2
-
Reserved
X
-
1
Bit 1
26, 27
DDR5(T&C)
Output Control
RW
DISABLE ENABLE
1
Bit 0
-
Reserved
X
-
1
Note:
Control Function
Affected Pin
BYTE
5
BYTE
6
PWD = Power Up Default
Type
Bit Control
Type
Control Function
Affected Pin
Bit Control
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ICS93732AFLFT | 功能描述:IC DDR PLL ZD BUFFER 28-SSOP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 专用 系列:- 标准包装:28 系列:- 类型:时钟/频率发生器 PLL:是 主要目的:Intel CPU 服务器 输入:时钟 输出:LVCMOS 电路数:1 比率 - 输入:输出:3:22 差分 - 输入:输出:无/是 频率 - 最大:400MHz 电源电压:3.135 V ~ 3.465 V 工作温度:0°C ~ 85°C 安装类型:表面贴装 封装/外壳:64-TFSOP （0.240"，6.10mm 宽） 供应商设备封装:64-TSSOP 包装:管件 |
| ICS93732AFT | 功能描述:IC DDR PLL ZD BUFFER 28-SSOP RoHS:否 类别:集成电路 (IC) >> 时钟/计时 - 专用 系列:- 标准包装:28 系列:- 类型:时钟/频率发生器 PLL:是 主要目的:Intel CPU 服务器 输入:时钟 输出:LVCMOS 电路数:1 比率 - 输入:输出:3:22 差分 - 输入:输出:无/是 频率 - 最大:400MHz 电源电压:3.135 V ~ 3.465 V 工作温度:0°C ~ 85°C 安装类型:表面贴装 封装/外壳:64-TFSOP （0.240"，6.10mm 宽） 供应商设备封装:64-TSSOP 包装:管件 |
| ICS93732FLF-T | 制造商:ICS 制造商全称:ICS 功能描述:Low Cost DDR Phase Lock Loop Zero Delay Buffer |
| ICS93732G-T | 制造商:ICS 制造商全称:ICS 功能描述:Low Cost DDR Phase Lock Loop Zero Delay Buffer |
| ICS93735 | 制造商:ICS 制造商全称:ICS 功能描述:DDR Phase Lock Loop Zero Delay Clock Buffer |
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