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参数资料
| 型号： | ICS93732YFLF-T |
| 元件分类： | 时钟及定时 |
| 英文描述： | 93732 SERIES, PLL BASED CLOCK DRIVER, 6 TRUE OUTPUT(S), 6 INVERTED OUTPUT(S), PDSO28 |
| 封装： | 0.209 INCH, ROHS COMPLIANT, MO-150, SSOP-28 |
| 文件页数： | 6/9页 |
| 文件大小： | 94K |
| 代理商： | ICS93732YFLF-T |
6
ICS93732
0578I—05/18/05
Bytes 0 to 4 are reseved power up default = 1. This allows operation with main clock.
Pin #
Name
0
1
PWD
Bit 7
2, 1
DDR0(T&C)
Output Control
RW
DISABLE ENABLE
1
Bit 6
4, 5
DDR1(T&C)
Output Control
RW
DISABLE ENABLE
1
Bit 5
-
Reserved
X
-
1
Bit 4
-
Reserved
X
-
1
Bit 3
13, 14
DDR2(T&C)
Output Control
RW
DISABLE ENABLE
1
Bit 2
17, 16
DDR3(T&C)
Output Control
RW
DISABLE ENABLE
1
Bit 1
-
Reserved
X
-
1
Bit 0
-
Reserved
X
-
1
Note:
Pin #
Name
0
1
PWD
Bit 7
-
Reserved
X
-
0
Bit 6
-
Reserved
X
-
0
Bit 5
-
Reserved
X
-
0
Bit 4
-
Reserved
X
-
1
Bit 3
24, 25
DDR4(T&C)
Output Control
RW
DISABLE ENABLE
1
Bit 2
-
Reserved
X
-
1
Bit 1
26, 27
DDR5(T&C)
Output Control
RW
DISABLE ENABLE
1
Bit 0
-
Reserved
X
-
1
Note:
Control Function
Affected Pin
BYTE
5
BYTE
6
PWD = Power Up Default
Type
Bit Control
Type
Control Function
Affected Pin
Bit Control
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| ICS93772AF | 功能描述:IC DDR PLL ZD BUFFER 28-SSOP RoHS:否 类别:集成电路 (IC) >> 时钟/计时 - 专用 系列:- 标准包装:1,500 系列:- 类型:时钟缓冲器/驱动器 PLL:是 主要目的:- 输入:- 输出:- 电路数:- 比率 - 输入:输出:- 差分 - 输入:输出:- 频率 - 最大:- 电源电压:3.3V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:28-SSOP（0.209"，5.30mm 宽） 供应商设备封装:28-SSOP 包装:带卷 (TR) 其它名称:93786AFT |
| ICS93772AFLF | 功能描述:IC DDR PLL ZD BUFFER 28-SSOP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 专用 系列:- 标准包装:1,500 系列:- 类型:时钟缓冲器/驱动器 PLL:是 主要目的:- 输入:- 输出:- 电路数:- 比率 - 输入:输出:- 差分 - 输入:输出:- 频率 - 最大:- 电源电压:3.3V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:28-SSOP（0.209"，5.30mm 宽） 供应商设备封装:28-SSOP 包装:带卷 (TR) 其它名称:93786AFT |
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