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参数资料
| 型号： | ICS93857YGLFT |
| 元件分类： | 时钟及定时 |
| 英文描述： | PLL BASED CLOCK DRIVER, 11 TRUE OUTPUT(S), 11 INVERTED OUTPUT(S), PDSO48 |
| 封装： | 6.10 MM, 0.50 MM PITCH, MO-153, TSSOP-48 |
| 文件页数： | 4/5页 |
| 文件大小： | 289K |
| 代理商： | ICS93857YGLFT |
4
ICS93857
Preliminary Product Preview
Notes:
1. Refers to transition on noninverting output in PLL bypass mode.
Tim ing Re quire m e nts
TA = 0 - 85C; Supply Vo ltage AVDD, VDD = 2 .5 V +/- 0 .2 V (u n less o th erwise stated )
PAR AM ETER
SYM B OL
C ONDITIONS
MIN
M AX
UNITS
Op erating clock freq uency
freq op
66
170
M Hz
Input clock duty cy cle
d tin
40
60
%
C LK stab ilizatio n
TSTAB
fro m VDD = 3 .3 V to 1 %
targ et freq .
100
s
Switching Characteristics
PARAMETER
SYMBOL
CONDITION
MIN
TYP
MAX
UNITS
Low-to high level propagation
delay time, bypass mode
tPLH
1
CLK_IN to any output
1.5
3.5
6
ns
High-to low level propagation
delay time
tPLL
1
CLK_IN to any output
1.5
3.5
6
ns
Output enable time
tEN
OE to any output
3
ns
Output disable time
tdis
OE to any output
3ns
Jitter; peak to peak jitter
Tjitter
100/125/133/167MHz
75
ps
Cycle to Cycle Jitter1
Tcyc-Tcyc
100/125/133/167MHz
75
ps
Phase error, static
t(phase error)
-150
150
ps
Output to Output Skew
Tskew
100
ps
Duty cycle
DC
2
100MHz to 167MHz
49
51
%
Rise Time, Fall Time
tr, tf
Load = 120
/16pF
800
950
ps
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| ICS93V855AG | 功能描述:IC DDR PLL CLOCK DRIVER 28-TSSOP RoHS:否 类别:集成电路 (IC) >> 时钟/计时 - 专用 系列:- 标准包装:1,500 系列:- 类型:时钟缓冲器/驱动器 PLL:是 主要目的:- 输入:- 输出:- 电路数:- 比率 - 输入:输出:- 差分 - 输入:输出:- 频率 - 最大:- 电源电压:3.3V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:28-SSOP（0.209"，5.30mm 宽） 供应商设备封装:28-SSOP 包装:带卷 (TR) 其它名称:93786AFT |
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