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参数资料
| 型号： | ICS93V857YG-25LFT |
| 元件分类： | 时钟及定时 |
| 英文描述： | PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48 |
| 封装： | 6.10 MM, 0.50 MM PITCH, MO-153, TSSOP-48 |
| 文件页数： | 6/10页 |
| 文件大小： | 214K |
| 代理商： | ICS93V857YG-25LFT |
5
ICS93V857-XXX
Preliminary Product Preview
Notes:
1.
Refers to transition on noninverting output in PLL bypass mode.
2.
While the pulse skew is almost constant over frequency, the duty cycle error increases at
higher frequencies. This is due to the formula: duty cycle=twH/tc, were the cycle (tc)
decreases as the frequency goes up.
3.
Switching characteristics guaranteed for application frequency range.
4.
Static phase offset shifted by design.
Timing Requirements
T
A = 0 - 85C; Supply Voltage AVDD, VDD = 2.5 V +/- 0.2V (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
MAX
UNITS
Max clock frequency
freq
op
2.5V+0.2V @ 25
oC
33
233
MHz
Application Frequency Range
freq
App
2.5V+0.2V @ 25
oC
60
170
MHz
Input clock duty cycle
d
tin
40
60
%
CLK stabilization
T
STAB
from VDD = 3.3V to 1%
target freq.
100
s
Switching Characteristics
PARAMETER
SYMBOL
CONDITION
MIN
TYP
MAX
UNITS
Low-to high level propagation
delay time
t
PLH
1
CLK_IN to any output
3.5
ns
High-to low level propagation
delay time
t
PLL
1
CLK_IN to any output
3.5
ns
Output enable time
t
EN
PD# to any output
3
ns
Output disable time
tdis
PD# to any output
3ns
66MHz
ps
100/125/133/167MHz
-75
75
ps
Half-period jitter
t(jit_hper)
100/133/167MHz
-100
100
Input clock slew rate
t(sir_I)
1
4
Output clock slew reate
t(sl_o)
1
4
66MHz
ps
100/125/133/167MHz
75
ps
Phase error
t
(phase error)
4
-50
0
50
ps
Output to Output Skew
T
skew
100
ps
Pulse skew
T
skewp
100
ps
66MHz to 100MHz
49.5
50.5
%
101MHz to 167MHz
49
51
%
Rise Time, Fall Time
tr, tf
Load = 120
/16pF
650
800
950
ps
Jitter period
T
jit (per)
D
C
2
Duty cycle
Cycle to Cycle Jitter1
T
cyc-Tcyc
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